Sanyo Electric Co., Ltd.

Wataru Andoh

Nobuyuki Sekikawa

Masaaki Momen

Koichi Hirata

Masaaki Anezaki

Noriyasu Katagiri

A gate electrode includes a first polysilicon film remaining on a first oxide film, a part of a second polysilicon layersuperimposed on the polysilicon layer, and a part of the second polysilicon layer partially extending over second gate oxide films. Thus, the thickness of the gate electrode on the first gate oxide film is the same as that of the gate electrode of the prior art, but the film thickness tof the gate electrodeon the second gate oxide filmsA andB is thinner than the thickness tof the prior art. Therefore, the height gap hbetween the gate electrodeand the N+type source layerand the height gap hbetween the gate electrodeand the N+type drain layerbecome smaller compared to those of prior art, leading to the improved flatness of the interlayer oxide film

Method of manufacturing insulated gate semiconductor device

When an element isolation film is formed by the LOCOS technique, as an underlying buffer layer of an oxidation resisting film, a pad oxidation film and pad poly-Si film are used. When an element is formed, they are used as a gate oxide film and a part of a gate electrode to relax a level difference between the gate electrode and the wiring on the element isolation film. A first poly-Si film (pad poly-Si film) is etched to leave its certain thickness to relax the level difference more greatly. In such a process, in manufacturing a semiconductor integrated circuit using the LOCOS technique, the number of manufacturing steps can be reduced and the level difference between the gate electrode on the gate insulating film and the wiring on the element isolation film can be relaxed.

Semiconductor device

A gate electrode includes a first polysilicon film remaining on a first oxide film, a part of a second polysilicon layer superimposed on the polysilicon layer, and a part of the second polysilicon layer partially extending over second gate oxide films. Thus, the thickness of the gate electrode on the first gate oxide film is the same as that of the gate electrode of the prior art, but the film thickness t of the gate electrode on the second gate oxide films A and B is thinner than the thickness t of the prior art. Therefore, the height gap h between the gate electrode and the N &plus; type source layer and the height gap h between the gate electrode and the N &plus; type drain layer become smaller compared to those of prior art, leading to the improved flatness of the interlayer oxide film

Insulated gate semiconductor device and its manufacturing method

To shorten the production process of the semiconductor device having the capacitance element. The pad oxide film ( ) and the first polycrystalline silicon layer ( ) are used as a stress buffering material at the time of formation of the element separation oxide film. These are not removed and used as the capacitance insulation film and a portion of the upper electrode of the capacitance element. Thereby, the removing process of the pad&bull;polycrystalline silicon layer, and the dummy oxidation and its removing process in the conventional example, can be omitted and the process can be shortened. Further, a problem of the impurity enhanced oxidation at the time of formation of the capacitance insulation film can be solved.

Semiconductor device having capacitance element and method of producing the same

Method of manufacturing semiconductor device and semiconductor device

To shorten the production process of the semiconductor device having the capacitance element. The pad oxide film (,) and the first polycrystalline silicon layer (,) are used as a stress buffering material at the time of formation of the element separation oxide film. These are not removed and used as the capacitance insulation film and a portion of the upper electrode of the capacitance element. Thereby, the removing process of the pad.polycrystalline silicon layer, and the dummy oxidation and its removing process in the conventional example, can be omitted and the process can be shortened. Further, a problem of the impurity enhanced oxidation at the time of formation of the capacitance insulation film can be solved.

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Niigata, Japan

Wataru Andoh