Silicon Laboratories Inc.

Other

Cirrus Logic Inc.

St-ericsson Sa

Wasim Quddus

Thomas Saroshan David

Jack B Andersen

Frederick Rush

Lionel Cimaz

David Anderton

Shaojie Chen

A semiconductor device that retains a state of a data storage element during a power reduction mode including supply rails and voltages, and a storage latch and a retention latch both powered by retention supply voltage that remains energized during a power reduction mode. The storage latch and the retention latch are both coupled to a retention node that is toggled between first and second states before entering the power reduction mode. The toggling causes the storage latch to latch the state of the data storage element during the normal mode, and the retention node enables the storage element to hold the state during the power reduction mode. The retention latch includes a retention transistor and a retention inverter powered by the retention supply voltage. The retention inverter keeps the retention transistor turned on and the retention transistor holds the state of the retention node during the power reduction mode.

State retention circuit that retains data storage element state during power reduction mode

A state retention circuit for retaining the state of a data storage element during a power reduction mode including a storage latch and a retention latch both powered by retention supply voltage that remains energized during a power reduction mode. The storage latch and the retention latch are both coupled to a retention node that is toggled from between first and second states before entering the power reduction mode so that the storage latch latches the state of the data storage element. The retention latch includes a retention transistor and a retention inverter powered by the retention supply voltage. The retention transistor is overpowered when the retention node is pulled to the second state in which the retention inverter quickly turns off the retention transistor. When the retention node is toggled back to the first state, the retention inverter keeps the retention transistor turned on during the power reduction mode.

Apparatus and methods for scanning a keypad of a communications device in a manner that tends to minimize interference with transceiver operation, such as a RF transceiver. In one embodiment, a controller receives a periodic signal of the communications device and provides a scan signal to cause the keypad to be scanned. In a sleep mode a keypad scan is performed only subsequent to a keypad activation. However, if the communications device is in use a keypad scan is performed once per frame at predetermined intervals, in one embodiment.

Keypad scanning with radio event isolation

A wireless communication device reduces undesired audio underflow in a digital to analog receive path that employs time domain isolation. One or more buffers in the receive path receive processed audio samples from a signal processor. A control circuit senses when the buffers in the receive path are substantially empty. In response to a substantially empty determination by the control circuit, the control circuit instructs one of the buffers to repeat the last processed audio sample which that buffer received to reduce or avoid audio underflow.

Wireless communication system including an audio underflow protection mechanism operative with time domain isolation

An apparatus and method for safely handling asynchronous shutdown of pulsewidth modulated output. A shutdown circuit controls asynchronous shutdown of a pulsewidth modulated stage to ensure that pulsewidth modulated signals of less duration than a minimum period does not occur at transition edges of the pulsewidth modulated signal, in which such short pulses may affect the proper operation of output circuitry.

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Austin, TX, United States of America

Wasim Quddus