Applied Micro Circuits Corporation

Intel Corporation

Waseem Saify Kraipak

George Bendak

Edward R Stanford

Jayesh Iyer

Sukanto Ghosh

Sunil Kumar Singla

Rajeev Ganesh

Pradeep Dharane

Yoon Sang Chae

In one embodiment a system comprises an integrated circuit, a plurality of voltage regulators; and a data bus coupled to the integrated circuit and the plurality of voltage regulators. In some embodiments the integrated circuit comprises logic to embed a timing signal on the data bus. Other embodiments may be described.

Two wire serial voltage identification protocol

Various aspects provide forced halt functionality for a processor to facilitate troubleshooting of processor hang situations. In the event that the processor initiates a transaction that does not receive a completion acknowledgement, a forced halt sequence can be initiated, which causes the processor to abort all pending transactions and transition to a debug state so that the internal state of the processor can be viewed. In addition, the processor can maintain a record of the processor state at the time that the hung transaction was dispatched, which can be viewed during debug mode to facilitate determining a cause of the hung transaction.

Debugging processor hang situations using an external pin

Various aspects provide forced halt functionality for a processor to facilitate troubleshooting of processor hang situations. In the event that the processor initiates a transaction that does not receive a completion acknowledgement, halt detection logic can initiate a forced halt sequence that causes the processor to abort all pending transactions and transition to a debug state so that the internal state of the processor can be viewed. In addition, the processor can maintain a record of the processor state at the time that the hung transaction was dispatched, which can be viewed during debug mode to facilitate determining a cause of the hung transaction.

Processor hang detection and recovery

A system and method are provided for using feedback to control processor frequencies in a system-on-chip (SoC). The method is associated with an SoC having a processor operating frequency responsive to a processor supply voltage on a first SOC interface, and a controller for managing the operating frequency. The controller accepts a frequency selection command associated with a first operating frequency, at a second SoC interface. The controller sends a first voltage command associated with the first frequency, via a third SOC interface, to a voltage regulator supplying the processor supply voltage. Then, the controller monitors the processor supply voltage. In response to detecting a processor first supply voltage, the processor is enabled to operate at the first frequency.

System-on-chip with feedback loop for processor frequency control

A system and method are provided for using a system-on-chip (SoC) memory manager to optimize the use of off-chip memory modules. A SoC memory controller receives a request for a first data block, subsequent to shutting the first memory down, and determines that the first data block is stored in the first memory. A SoC memory switching core uses a memory map to translate the first data block address in the first memory module to a first data block address in the second memory module. If the first data block is present in an on-SoC cache, the first data block is supplied on the SoC data bus from the cache. Then, the cache is loaded with a plurality of data blocks from a corresponding plurality of addresses in the second memory module, associated with the first data block address.

Dynamic memory module switching with read prefetch caching

A system and method are provided for using a thermal management core to control temperature on a system-on-chip (SoC). The method provides an SoC with an internal thermal management core and an internal temperature sensor. For example, the sensor may be located on or near a processor core die. The thermal management core monitors temperatures recorded by the SoC temperature sensor, and sends commands for controlling SoC device functions. In response to these commands, the thermal management core monitors a change in the temperature at SoC temperature sensor. The temperature sensor may be monitored via a dedicated SoC internal interface connecting the processor and the thermal management core. Alternately, the thermal management core may poll for temperatures via a system management bus (SMBUS) SoC external interface connecting the processor and thermal management core. Further, a dedicated SoC external alert interface connecting the processor and thermal management core may be monitored.

System-on-chip with thermal management core

A system and method are provided for adaptively configuring L2 cache memory usage in a system of microprocessors. A system-on-chip (SoC) is provided with a plurality of n selectively enabled processor cores and a plurality of n L2 cache memories. The method associates each L2 cache with a corresponding processor core, and shares the n L2 caches between enabled processor cores. More explicitly, associating each L2 cache with the corresponding processor core means connecting each processor core to its L2 cache using an L2 data/address bus. Sharing the n L2 caches with enabled processors means connecting each processor core to each L2 cache via a data/address bus mesh with dedicated point-to-point connections.

System and method for adaptively configuring an L2 cache memory mesh

A system and method are provided for a system-on-chip (SoC) management module to monitor and dynamically control processor core operating voltages. An SoC is provided with a plurality of processor cores, a plurality of voltage regulators, an internal management module, and at least one temperature sensor. The management module compares monitored temperatures to threshold values, and in response generates voltage commands. The management module sends the voltage commands to the voltage regulators. Each voltage regulator adjusts the operating voltage supplied to a corresponding processor core in response to the voltage commands.

System-on-chip with management module for controlling processor core internal voltages

A system and method are provided for using a system-on-chip (SoC) memory manager to dynamically shutdown and restart an off-chip memory module. After determining that a memory switch is to be enacted, an SoC memory switching core asserts a hold on processor operations. The memory switching core transfers data from a source memory module to a destination memory module. In a shutdown operation, data is transferred from a first memory module source to an external second memory module destination interfaced to the memory switching core. In a restart operation, data is transferred from the second memory module source to the first memory module destination. The memory switching core uses a memory map for translating the data addresses in the source memory module to data addresses in the destination memory module. Then, the memory switching core deasserts the hold on processor operations.

System-on-chip with dynamic memory module switching

A system and method are provided for using a system-on-chip (SoC) memory speed control logic core to control memory maintenance and access parameters. A SoC is provided with an internal hardware-enabled memory speed control logic (MSCL) core. An array of SoC memory control parameter registers is accessed and a set of parameters is selected from one of the registers. The selected set of parameters is delivered to a SoC memory controller, to replace an initial set of parameters, and the memory controller manages an off-SoC memory using the delivered set of parameters.

System-on-chip with memory speed control core

According to some embodiments, a method and system are provided to initiate communication at an integrated circuit that is electrically coupled to a plurality of voltage regulators, determine a slowest one of the plurality of voltage regulators that is electrically coupled to the integrated circuit, and communicate with the plurality of voltage regulators that are electrically coupled to the integrated circuit at a speed associated with the slowest one of the plurality of voltage regulators.

Time negotiation using serial voltage identification communication

According to some embodiments, a method and system are provided to initiate communication at an integrated circuit that is electrically coupled to a plurality of voltage regulators, determine a slowest one of the plurality of voltage regulators that is electrically coupled to the processor, transmit address information to the plurality of voltage regulators that are electrically coupled to the processor at a first speed associated with the slowest one of the plurality of voltage regulators, determine a second speed associated with a voltage regulator to which the address information is associated, and transmit a second portion of the packet at the second speed associated with the voltage regulator to which the address information is associated.

Data negotiation using serial voltage identification communication

A system and method are provided for in-network power management of network-connected devices. A first computing device, having a power management module, is able to access an in-network computing device table stored in a local memory, of network-connected computing devices cross-referenced to computing device processing capabilities. The power management module retrieves processing capabilities from the in-network computing device table for a network-connected second computing device, and sends a Wake-on-Local Area Network (LAN) message to the second computing device. Subsequently, the power management module sends a server-on-cloud power management message (power management packet) to the second computing device, with instructions for enabling capabilities related to processing or memory management.

Growing community of inventors

Maharastra, India

Waseem Saify Kraipak