International Business Machines Corporation

Warren W Grunbok

Donald W Price

De Tran

Jeb R Linton

Dale E Pontius

Mark Elliott Hack

Billy J Knowles

Robert Tamlyn

Yee-Ming Ting

William R Milani

Henry Yeh

Douglas R Moran

Harmeet Singh

Rosana Ramos Morales

Described are techniques for a secure roles-based access control (RBAC) setup during boot of a connected computational system. The techniques include a method comprising deploying a preconfigured default user profile during booting of a computational system. The techniques further include creating, using the preconfigured default user profile, a plurality of user profiles having administrator and/or root authorities, where each of the plurality of user profiles is associated with a respective custom password. The techniques further include completing booting of the computational system using the plurality of user profiles having the administrator and/or root authorities.

Secure preconfigured profile for role-based access control setup

A trusted computing environment may be dynamically certified by providing a selectable boot option that controls running a loadable boot image in one of a test mode and a production mode. The test mode may automate running a processing standard validation test to obtain a processing standard validation test result. Responsive to running the processing standard validation test with a successful test result, a record indicating the successful test result and the loadable boot image is stored within the trusted computing environment, utilizing a certification process. Responsive to running the production mode, the trusted computing environment and the loadable boot image may be loaded.

Trusted computing attestation of system validation state

A stride enhancer provides high memory bandwidth on strides greater than one and minimizes requests to memory. The basic memory module (BSM) design uses line fetches as the basic cache complex fetch mechanism and allows operation of the BSM to be stride independent. In the preferred implementation, the BSM has two fetch modes; a normal mode and a line fetch mode. In the normal mode, a quadword (QW) is fetched as in the conventional design. In the line fetch mode, all double words (DWs) within the referenced line are returned to the storage control element (SCE) at two DWs per cycle for strides one through eight (twice the conventional bandwidth) or at least one DW per cycle for all other strides (equal to the conventional bandwidth). This is accomplished with two DW busses rather than a single QW bus and by interleaving DW storage locations within the BSM. In line fetch mode for strides one through eight, DWs are read out according to the stride on the two DW busses.

Stride enhancer for high speed memory accesses with line fetching mode

A memory system and a unique memory chip is disclosed wherein multiple islands on a chip can be separately accessed by separate island controllers whereby concurrent use of the several islands or arrays on a chip can be achieved.

Memory system and unique memory chip allowing island interlace

Growing community of inventors

Poughkeepsie, NY, United States of America

Warren W Grunbok