Cypress Semiconductor Corporation

Monterey Research, LLC

Cypress Microsystems, Inc.

Warren S Snyder

Harold Kutz

Monte F Mar

Timothy John Williams

Bert Sullam

David Gordon Wright

Eashwar Thiagarajan

Mark E Hastings

Dennis Raymond Seguine

Haneef D Mohammed

James H Shutt

Bruce E Byrkett

Nathan Wayne Kohagen

Kenneth Y Ogami

Gajender Rohilla

Eric D Blom

Craig Nemecek

Mark W Rouse

Melany Ann Richmond

Jeffrey Erickson

Dinesh Maheshwari

David Van Ess

Matthew A Pleis

Thurman John Rodgers

Scott Allen Swindle

Andrew C Page

John B Foreman

Drew Marshall Harrington

Greg Verge

Frederick D Jaccard

Robert Walter Metzler, Jr

Tim Williams

Louis Cambre

Bijan Kamran

A microcontroller comprises a plurality of digital peripheral blocks and a direct memory access (DMA) controller coupled thereto. The plurality of digital peripheral blocks includes a digital peripheral block that is configured to issue a DMA request. Upon receipt of the DMA request, the DMA controller is configured to retrieve configuration information and to write the configuration information to a configuration register associated with a circuit element of the microcontroller.

Combined analog architecture and functionality in a mixed-signal array

A method for operating a system level interconnect in an integrated circuit (IC) is provided in an example embodiment. The method comprises: writing, by a microcontroller in the IC, a first configuration value into a configuration register, where the first configuration value programs the system level interconnect to couple a first peripheral to a second peripheral; monitoring the IC to determine an operational state of the IC; and in response to determining a change in the operational state of the IC, writing by the microcontroller a second configuration value into the configuration register to dynamically change interconnections in the system level interconnect between the first peripheral and the second peripheral.

System level interconnect with programmable switching

A programmable device, having an analog component coupled with an analog bus and a digital component coupled with a digital bus together with a set of 10 pads, each of which capable of being coupled to a bus line of one segment of the analog bus as well as to at least one digital bus line, and where the analog bus is capable of being used to connect a pair of the pads to each other.

Bus sharing scheme

Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming information stored in the memory components. Programmable interconnect logic, also programmable from the memory components, is used to couple the programmable analog and digital blocks as needed. The advanced microcontroller design also includes programmable input/output blocks for coupling selected signals to external pins. The memory components also include user programs that the embedded microprocessor executes. These programs may include instructions for programming the digital and analog blocks 'on-the-fly,' e.g., dynamically. In one implementation, there are a plurality of programmable digital blocks and a plurality of programmable analog blocks.

Microcontroller programmable system on a chip

A method and system of automatically generating source code for configuring a programmable microcontroller. The method involves displaying virtual blocks in a computerized design system where the virtual blocks correspond to programmable circuit blocks in a microcontroller chip. The user selects a user module that defines a particular function to be performed on the microcontroller. The user assigns the virtual blocks to the user module. The design system then automatically generates source code for configuring the programmable blocks to perform the desired function. The source code can then be assembled, linked and loaded into the microcontroller's memory system. When executed on the microcontroller, the executable code will then set registers within the blocks to implement the function. Source code is automatically generated for: (1) realizing the user module in a hardware resource; and also (2) to configure the user module to behave in a prescribed manner.

System providing automatic source code generation for personalization and parameterization of user modules

A programmable device comprises a plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, and a power manger coupled with the plurality of programmable blocks. The power manager is configured to supply power to a subset of the plurality of programmable blocks during debugging of the subset while maintaining a different subset of the plurality of programmable blocks in a lower power mode.

In an example embodiment, a digital block comprises a datapath circuit, one or more programmable logic devices (PLDs), and one or more control registers. The datapath circuit comprises structural arithmetic elements. The one or more PLDs comprise uncommitted programmable logic. The one or more control circuits comprise a control register configured to store user-defined control bits, where the one or more control circuits are configured to control both the structural arithmetic elements and the uncommitted programmable logic based on the user-defined control bits.

An example semiconductor chip includes analog circuits, digital circuits, and a digital input port. The digital input port is to receive an input signal. The analog circuit is to receive the input signal from the digital input port and produce a digital signal based on the input signal.

PSoC architecture

A programmable device comprises a plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, and a power manager coupled with the plurality of programmable blocks. The power manager is configured to supply power to a subset of the plurality of programmable blocks during debugging of the subset while maintaining a different subset of the plurality of programmable blocks in a lower power mode.

A circuit with a plurality of analog circuit blocks, each configured to provide at least one analog function and a programmable interconnect coupled of the analog circuit blocks and configurable to interconnect combinations of the analog circuit blocks to one another. The circuit is formed in an integrated circuit (chip) and the programmable interconnect comprises a plurality of switches coupled between the analog circuit blocks and ports that provide signal connections for the chip.

PSOC architecture

A programmable device includes reconfigurable analog circuitry, reconfigurable digital circuitry, a plurality of input/output (I/O) blocks, and a global mapping system. The global mapping system is configured to selectively couple the plurality of I/O blocks with analog functional units of the reconfigurable analog circuitry and with digital functional units of the reconfigurable digital circuitry.

Microcontroller programmable system on a chip with programmable interconnect

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Snohomish, WA, United States of America

Warren S Snyder