Altera Corporation

Warren Nordyke

Yan Chong

Weiqi Ding

Khai Nguyen

Gordon Raymond Chiu

Sean Shau-Tu Lu

Chiakang Sung

Bonnie I Wang

Navid Azizi

Wilma Waiman Shiao

Krzysztof Maryan

Pradeep Nagarajan

Ee Mei Ooi

Weizhong Xu

James Kimble Lin

In one aspect, a method includes receiving a differential strobe signal including first and second components; buffering, by a first buffer, both the first and second components; and buffering, by a second buffer, the first component. The method includes receiving, by a control logic block, the output of the second buffer. The method includes, after a period when the values of both the first and second components are at a first logic state, but before receiving a burst of clock edges in the differential strobe signal, detecting a transition in the first component from the first logic state to a second logic state, and in response to the detected transition, asserting an enable signal. The method further includes receiving, by a gating logic block, the enable signal and the output of the first buffer, and, when the enable signal is asserted, un-gating the output of the first buffer.

Circuits and methods for DQS autogating

Integrated circuits may include memory interface circuitry operable to communicate with system memory. The memory interface circuitry may receive data (DQ) and data strobe (DQS) signals from system memory during read operations. The memory interface circuitry may include startup calibration circuitry and runtime calibration circuitry. The startup calibration circuitry may be used upon device startup to perform a one-time data de-skew and DQ/DQS centering. The runtime calibration circuitry may include at least two data sampling circuits, a first of which is used in active mode to latch incoming data and a second of which is used in redundant mode to obtain data eye boundary information on a continuous basis. The received DQS signal may be adjusted based on the obtained eye boundary information so that DQS properly positioned within the data eye periodically or on an as-needed basis.

Methods and apparatus for performing runtime data eye monitoring and continuous data strobe calibration

An integrated circuit such as a programmable integrated circuit may include input-output circuits each having respective memory controller circuitry. The memory controller circuitry of the input-output circuits may be electrically coupled via a backbone path and configured to collectively form a memory controller. Each memory controller circuitry may include a protocol control circuit and input-output lanes. Memory access requests from on-chip circuitry may be provided to only a selected input-output circuit. The protocol control circuit of the selected input-output circuit may receive the memory access requests and generate memory control signals and local control signals from the memory access requests. The memory control signals may be provided to external memory. The local control signals may be provided to input-output circuits over the backbone path and synchronize the input-output circuits in conveying data between the integrated circuit and the external memory.

Integrated circuits having input-output circuits with dedicated memory controller circuitry

Integrated circuits may include memory interface circuitry that communicates with memory. The memory interface circuitry may include latch circuitry that receives a data strobe enable signal from the memory controller and latches the data strobe enable signal using a data strobe signal received from the memory. The integrated circuit may include logic circuitry that gates the data strobe signal using the latched data strobe enable signal. The logic circuitry may pass the data strobe signal in response to activation of the latched data strobe enable signal. The integrated circuit may include counter circuitry that monitors the gated data strobe signal. The counter circuitry may monitor the gated data strobe signal by counting pulses in the gated data strobe signal to produce a counter value. When the counter value reaches a target value, the logic circuitry may block the data strobe signal from passing to the memory controller.

Memory interface circuitry with improved timing margins

An integrated such as a programmable integrated circuit may include input-output pins that have associated input-output circuits. An input-output circuit may include memory interface circuits, clock recovery interface circuits, shared interpolator circuitry, and selection circuitry that may be configured to convey control signals from selected interface circuits to the shared interpolator circuitry. The interpolator circuitry may receive multiple clock signals and perform phase interpolation operations on the clock signals based on the selected control signals to produce modified clock signals. The modified clock signals may be used by the selected interface circuits for communications over the input-output pins. Logic design computing equipment such as computing equipment having CAD tools may be used to configure the selection circuitry.

Input-output circuitry for integrated circuits

A frequency divider circuit includes an adder circuit, multiplexer circuits, and a phase interpolator circuit. The adder circuit generates a summed value. The multiplexer circuits receive first periodic signals and generate second periodic signals by selecting among the first periodic signals based on the summed value. The phase interpolator circuit generates a third periodic signal using a weighted average of the second periodic signals that is determined based on the summed value.

Techniques for dividing frequencies of periodic signals

An integrated circuit may include memory interface circuitry that is used to communicate with off-chip memory. The memory interface circuitry may include data strobe (DQS) enable circuitry that receives DQS signals from the off-chip memory and that outputs a gated version of the DQS signals. The DQS enable circuitry may include an input buffer, a comparator, a latch, a flip-flop, a counter, and a gating circuit. The input buffer may receive an incoming DQS signal. The comparator may be used to determine when the incoming DQS signal starts to toggle. The latch may be used to control when a gating signal is asserted. The flip-flop controls the counter, which limits the duration that the gating signal is asserted. The gating circuit receives the DQS signal from the buffer and the gating signal and passes the DQS signal through to its output only when the gating signal is asserted.

Data strobe enable circuitry

Clock alignment circuitry may include phase comparator circuitry with a first input terminal that receives as first clock signal from a first clock tree and a second input terminal that receives a second clock signal from a second clock tree. The phase comparator circuitry may compare the first and second clock signals and generate different control signals based on the first and second clock signals. The integrated circuit may further include phase interpolator circuitry that generates an output clock signal based on at least one of the control signals received from the phase comparator circuitry. Edges of the generated output clock signal may align with edges of either the first clock signal or the second clock signal.

Methods and apparatus for clock tree phase alignment

A circuit includes first and second bidirectional clock networks and first and second clock signal generation circuits. A first multiplexer circuit is configurable to provide a first clock signal from a first pin to the first bidirectional clock network. A second multiplexer circuit is configurable to provide the first clock signal from the first bidirectional clock network to the second bidirectional clock network. Third multiplexer circuits are configurable to provide the first clock signal from the second bidirectional clock network to the first and the second clock signal generation circuits.

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Cupertino, CA, United States of America

Warren Nordyke