Ltx Corporation

Warren Necoechea

Mark E Deome

Michael Carlyle Davis

Timothy Alton

Wai-Kong Chen

Henk Zantman

Tim Alton

A method is described for facilitating use of a first pattern utilizing XOR data formatting in an electronic tester. The method includes dividing the first pattern into at least a first group and a second group, the tester to successively execute the first group and the second group. The method further includes assuming an entry state for each group is one of two binary conditions and inverting programmed commands for the second group if an ending state of the first group is not equal to the assumed entry state.

Pattern correction circuit

A phase-locked loop circuit having a programmable tuning voltage. As the input reference clock frequency is changed, the tuning voltage is changed accordingly to compensate for the propagation delay through the phase detector and thereby reduce discrepancies in the phase relationship between the input reference clock signal and the output clock signal at different frequencies. A set of compensation values corresponding to input reference clock frequencies are stored in a memory device. When the input reference clock frequency is changed, a corresponding compensation value is programmed to a digital-to-analog converter (DAC). The DAC outputs a voltage that is proportional to the value of the digital input to the DAC and can thus be used to regulate the tuning voltage of the PLL circuit so that the relationship of the input reference clock signal to the output clock signal remains stable with frequency changes.

Methods and apparatuses for digitally tuning a phased-lock loop circuit

Growing community of inventors

Scotts Valley, CA, United States of America

Warren Necoechea