Marvell International Limited

Warren Menezes

Hunglin Hsu

Viney Gautam

Yicheng Guo

Joshua R Smith

A circuit includes an instruction scheduling circuit and an instruction buffer including entries. The entries each include an instruction, a validity indication, and an attribute. The instruction scheduling circuit partitions the entries into first sets, determines second sets by reordering the entries of each first set according to their attributes, determines a set ordering for the first sets according to a function of their attributes, and selects, based on the set ordering, instructions from the second sets. A process for selecting instructions to issue receives entries, each entry including an instruction, a validity indications, and an attribute. The process partitions the entries into first sets, determines second sets by reordering the entries of each first set according to their attributes, determines a set ordering for first sets according to a function of the attributes of their entries, and selects, based on the set ordering, instructions from the second sets.

Selection of instructions to be issued

An apparatus comprises an event memory to store one or more events, and a prefetch circuit. The prefetch circuit a) detects a current stride between a first address and a second address, b) detects a stride break using the current stride and a stride of a first dimension, and c) stores a first event in the event memory when the stride break is detected. The first event includes i) an event address corresponding to the first address, and ii) a stride corresponding to the current stride. A method for generating a prefetch address comprises detecting, by a prefetch circuit, a first stride break between a first address of a stream and a second address of the stream, storing, in the prefetch circuit, a first event corresponding to the first stride break; and generating, by the prefetch circuit, an output prefetch address using the stored first event.

Multi-dimensional prefetching

In aspects of determining memory access patterns for cache prefetch in an out-of-order processor, data is maintained in a cache when copied from system memory of a computing device, and load data instructions are processed to access the cache data. The load data instructions include incremental load data instructions and non-incremental load data instructions that access the data from contiguous memory addresses. The data is prefetched ahead of processing the load data instructions, where prefetch requests are initiated based on the load data instructions. A stride is calculated as the distance between the incremental load data instructions. Further, the stride can be corrected for the non-incremental load data instructions to correlate with the calculated stride. The corrected stride represents the data as a sequential data stream having a fixed stride, and prefetching the data appears sequential for both the incremental and non-incremental load data instructions.

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Warren Menezes