Hewlett-packard Company

Warren M Uesato

Hung-Kwei Hu

Leuh Fang

Jung Lin

Paul K Aum

Kwang-Leei K Young

During the manufacture of a semiconductor integrated circuit, contact holes or passages are formed through a non-planar insulating layer resulting from the deposition of dielectric over electrical contacts having differing profile heights from the surface of an internal layer, such as a substrate, to expose these contacts and/or provide electrical connections thereto. The passages are formed with a combination of sloped and vertical sidewall portions in which varying depth sloped portions are used to effectively planarize the dielectric layer and permit the vertical sidewall portions to have substantially identical vertical dimensions. This technique simultaneously exposes contacts with varying profile heights which thereby reduces contact damage. In addition, this technique effectively planarizes the dielectric layer, reducing the need for an additional planarization step.

Simultaneous dielectric planarization and contact hole etching

A method of forming an interconnect, particularly a local interconnect, for a silicon substrate having integrated circuit devices between dielectric regions. Titanium disilicide is formed on electrode regions of the integrated circuit devices, whereafter titanium-tungsten is deposited across the silicon substrate. A photomask is formed and patterned to cover selected portions of the titanium-tungsten layer. The uncovered portions receive a preliminary etch of chlorine and carbon tetrafluoride to remove oxide. A second etch using trifluoromethane and oxygen removes the uncovered portions, leaving an electrically conductive interconnect extending from an electrode region onto a dielectric region leading to a second electrode region. The photomask is then removed.

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San Jose, CA, United States of America

Warren M Uesato