Texas Instruments Corporation

Warren L Bean

Shivaling S Mahant-Shetti

George R Doddington

Derek J Smith

Basavaraj I Pawate

Thomas J Aton

Mark G Harward

Memory chips with data memory (202), embedded logic (206) and broadcast memory (204) for two modes of operation are disclosed. A first mode of operation is the usual memory mode expected of a data RAM. The second mode of operation allows localized computation and/or processing of the data in data memory (202) by the embedded logic (206) with minimal handshaking with a remote CPU. In a functioning system, the memory chips are organized in a hierarchical manner and include address-associative memory systems.

Distributed processing memory chip with embedded logic having both data

A memory system 10 is provided including a processor 12 and an active memory device 14 coupled to a processor 12. Active memory 14 includes a first memory 20 for storing a plurality of possible addresses and a second memory 22 for storing an actual address received from processor 12. Circuitry 26 is provided for identifying at least one active address from ones of the possible addresses stored in first memory 20 as a function of the actual address stored in second memory 22.

Devices, systems and methods for implementing a Kanerva memory

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Austin, TX, United States of America

Warren L Bean