Hewlett-packard Development Company, L.P.

Hewlett-packard Company

Warren Kurt Howlett

Brian William Hughes

J Michael Hill

Christopher L Lyles

Jonathan E Lachman

Systems and methods for accessing common registers in a multi-core processor are disclosed. In an exemplary embodiment a method may comprise streaming at least one transaction from one of a plurality of processing cores in a core domain directly to a register domain. The method may also comprise reassembling the at least one streamed transaction in the register domain for data access operations at the common registers.

Accessing common registers in a multi-core processor

Systems and methods for accessing common registers in a multi-core processor are disclosed. In an embodiment a method may comprise streaming at least one transaction from one of a plurality of processing cores in a core domain directly to a register domain. The method may also comprise reassembling the at least one streamed transaction in the register domain for data access operations at the common registers.

Systems and methods of accessing common registers in a multi-core processor

In one aspect, the present invention features techniques for generating a repair solution for a memory having a set of IOs including a plurality of main IOs and a plurality of redundant IOs. For example, techniques are provided for selecting a mapping between input/output ports of the memory and a subset of the memory's IOs. In particular, techniques are provided for configuring a plurality of multiplexors to implement the selected mapping by establishing electrical connections between the subset of IOs and the memory input/output ports. The subset of IOs may include one or more of the plurality of redundant IOs which effectively replace one or more defective ones of the main IOs. The plurality of multiplexors may be configured by generating one or more thermometer codes which encode the identities of any defective main IOs and which serve as selection inputs to the plurality of multiplexors.

Repair techniques for memory with multiple redundancy

The present invention is directed to a system and method which manages one or more errors in a plurality of elements. The invention tests an element of the plurality of elements and detects the error in one of the elements. The invention then repairs a group of N elements, wherein N is greater than one and the group of N elements includes the element with the error. The invention inhibits subsequent repairs of the group of N elements.

Device to inhibit duplicate cache repairs

The invention provides a circuit and method for obtaining a fully functional microprocessor using only a fraction of the available on-chip cache. The memory sub-arrays of the on-chip cache are tested to determine which sub-arrays are functional. After determining which sub-arrays are functional, a set of sub-arrays is selected that constitute a binary fraction of the cache. The CPU is initialized to accommodate a smaller address space corresponding to the size of the selected sub-arrays. Finally, a group of signals are programmed to allow the CPU access to the selected sub-arrays.

Method and apparatus for achieving higher product yields by using fractional portions of imbedded memory arrays

The present invention incorporates built-in self test and self repair functionality into a semiconductor memory device in which reconfiguration data used to replace faulty memory is stored at the same time testing to identify other faulty memory cells continues. To avoid access contention conflicts to a content addressable memory used to identify rows or groups of rows having faulty memory cells, the built in test function writes test data to each cell at least twice before reading the stored data. By writing twice before reading, contention problems caused by simultaneous updating of the content addressable memory are avoided. That is, even if the content addressable memory is initially unavailable to process address information used to access a memory cell to be tested, repetition of the write process ensure that the data will be properly stored when the memory again becomes available after being updated.

Cache test sequence for single-ported row repair CAM

The most significant N bits of each number in a pseudo random sequence are generated by unidirectionally shifting the previous bits from a first memory cell toward the Nth memory cell of a sequential register and generating a new bit in the first memory cell in response to a predetermined combination of the previous N bits through feedback logic, for example by NORing the previous N most significant bits, such that always at least one of the N bits is a zero. N most significant bits are matched with a least significant bits portion that cycles exactly once for each most significant bit value. This results in a pseudo random sequence excluding an upper fraction of one-fourth, one-eighth, . . . , (one-half) of an otherwise power of two range. Embodiments include right or left shifting, generating reversed sequences, or coupled right- and left-shifting, in hardware or software implementations.

Pseudo random address generator for 0.75M cache

M parallel datastreams are interleaved into a serial bitstream and shifted into a staging register, so that bit zeros of all datastreams shift in first and bit (X-1)s last. All bits of the Mth datastream occupy uniformly spaced non-adjacent memory elements interconnected with a target memory device having M memory registers each of width X. The Mth memory register of the memory device is addressed, simultaneously writing all interconnected bits to the Mth memory register within a single clock period. The bitstream is then shifted by one memory element, such that bits of the (M-1)th parallel datastream occupy the interconnected memory elements, the register address decrements, and the interconnected bits are simultaneously written to the (M-1)th register. This process iterates until M registers are written within an elapsed time of M clock periods. Reading occurs essentially in a reverse sequence.

Read/write eight-slot CAM with interleaving

The present invention includes a system and a methodology for eliminating faulty memory cells in a memory array with replacement columns of memory cells and replacement rows of memory cells. The individual memory cells are checked to ensure that each is operational. Non-operational cells are replaced by first replacing columns which contain a threshold number of non-operational cells with spare columns and second removing any remaining non-operational cells by replacing the rows containing those non-operational cells with spare rows.

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Windsor, CO, United States of America

Warren Kurt Howlett