Lexmark International, Inc.

International Business Machines Corporation

Warren J Spina

Stephen R Troyer

Jeffrey A Minnick

James Ronald Booth

John Parker Richey

Brian Wesley Damon

Cuong Manh Hoang

Carl P Cole

Lynn M Oliver

James L Beck

Terry Lee Parker

Terry W Ringle

Sean Foster Garnett

Larry Wayne True

An ASIC (5) has four driver circuits (19a-19d), each with different output power. One of those driver circuits is selected from the content of register (13) on the ASIC. The register content being decoded by a decoder (15) on the ASIC to a signal which activates a single one of the drivers. The register is loaded from an external microprocessor during each initialization of a printer (1) in which the ASIC is a component. The ASIC is designed with the range of the powers of the drivers bracketing the estimated needs of the load to be attached to the ASIC. This permits the ASIC to be completed only once, while the most suitable driver for the final load is determined subsequently and selected by the entry of data to activate that driver into the register with each initialization of the printer. The ASIC need not have nonvolatile memory and only a single set of ASIC masks and other design aspects need be completed.

ASIC with selectable output drivers

A clock circuit (12) normally couples clock pulses to a microprocessor (11), which is capable of accessing memory devices (13,14) having different access times. Access of a 'slow' memory device 14 is detected by the clock circuit, and in response thereto, one or more clock pulses are not coupled to the microprocessor. This suspends operation of the microprocessor for a suitable amount of time so that the microprocessor reads valid data from the slow memory device. The number of clock pulses blocked from reaching the microprocessor can be set in a delay circuit (28) in the clock circuit.

Digital processor clock circuit

A page printer (101) which rasterizes a page utilizing partial page bit map swaths. Received data to be printed is stored in packets (12-17) in a page buffer in random access memory (105). Data within each packet is arranged in printing order down the page to be printed, but the packets themselves are arranged in the order received, and are not indexed or linked. As each swath (11) is rasterized, each packet is examined, and packets containing data falling at least in part within the active swath are processed. The printer is controlled by a programmed microprocessor, and logic hardware assistance is provided for translating data addresses from logical addresses (54) to physical addresses (52). Logic hardware assistance is also provided for making the determination of whether or not a given data address lies within the active swath.

Printer buffer and rasterization arrangement

A printer having a print engine (13) and a bit map memory (12) including a number of page image areas (31) into which information to be printed is rasterized and from which information for the print engine is serialized. A digital processor (11) controlling the print engine is operable to reduce a page image area (31) to a modified page image area (37) based upon the highest and lowest addresses at which information has been written into the page image area. The digital processor (11) is also operable to begin rasterization of a new page image area when a sufficient amount of an existing page image area (41) has been serialized to make available the requisite bit map memory for the new page.

Bit map memory management for a page printer

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Lexington, KY, United States of America

Warren J Spina