Pitney Bowes Inc.

Other

Warren G Hafner

Peter C DiGiulio

Henry Stalzer

John R Lowdenslager

An electronic postage meter with a non-volatile memory security circuit apparatus is disclosed. The security circuit comprises means for limiting the amount of time the memories may be continuously enabled, means for preventing simultaneous enabling of both memories and means for preventing the write enabling of a memory if the write enable signal is active before a memory select signal is active. The circuit prevents memory access when a conflict is sensed across in an output related to the non-volatile memories. The security circuit provides additional protection to the non-volatile memory so that valuable critical accounting information located therein cannot be modified or destroyed.

Postage meter with a non-volatile memory security circuit

A voltage regulator fabricated on an integrated circuit chip to provide regulated voltage for the chip assures that the integrated chip is operational before conventionally provided external regulated voltages are available. This enables the integrated circuit chip to be used to monitor the external regulated voltage supplies and prevents latch-up of the integrated circuit due to improper voltages being applied during power sequencing.

On-chip voltage supply regulator

A low voltage control circuit, and associated method, is provided for maintaining at least one output terminal in a known state regardless of the state of the inputs, when at least one voltage to be monitored is above a threshold voltage and below a predetermined limit voltage, comprising control means for providing a deactivating output voltage when the voltage to be monitored is below the predetermined limit voltage, output means electrically coupled to the control means for receiving the output voltage from the control means and for receiving at least one input voltage, the output means being deactivated in response to the deactivating output voltage to provide a known voltage state at the output terminal until the voltage to be monitored reaches the predetermined limit voltage whereupon the control means will provide an activating output voltage to the output means to enable the voltage state at the output terminal to be controlled by the state of the inputs.

Circuit for maintaining the state of an output despite changes in the

A method and apparatus for providing enhanced security to the non-volatile memory of an electronic postage meter during power up and power down of the meter is disclosed. The apparatus comprises means for detecting a regulated voltage level of the meter, means for detecting an unregulated voltage level of the meter, means for detecting a predetermined frequency from a system clock associated with the meter and a reset delay circuit responsive to the detected unregulated voltage, detected regulated voltage and the predetermined clock frequency for allowing access to the non-volatile memories if the unregulated voltage level, the regulated level and the clock frequency have reached their appropriate levels and preventing access to the memories otherwise. Through the use of this circuitry the critical accounting information within the memories is protected during the powering up and powering down of the postage meter.

Electronic postage meter having power up and power down protection

A short circuit protection circuit and associated method is provided, for a device with a first and second power supply. The circuit comprises a pair of switches connected to the respective power supplies, a current sensing element connected to each switch and an output buffer circuit connected to each switch for preventing either power supply from being shorted. The circuitry utilizes advantageously integrated circuit technology. Through the use of the circuitry the power supplies are effectively removed from the output buffer when excessive current is sensed.

Multiple power supply overcurrent protection circuit

An electronic postage meter with a circuit to provide for a delay period before operation of a postage meter is disclosed. The circuit provides a fixed delay which is triggered when three input signals provided to the circuit become active. The input signals will be active in this embodiment to indicate satisfactory regulated voltage level, a satisfactory unregulated voltage level, and a satisfactory external clock frequency respectively. The output of the delay circuit upon acceptance of these active signals provides a reset delay signal to a system processor and also controls the signals that are provided to the non-volatile memories and the system printer. The circuit uses advantageously logic devices to provide the delay of the output signal rather than the traditional utilization of R-C network. The delay circuit is particularly useful in a system such as postage meter that utilizes a microprocessor and a non-volatile memory, to protect the contents of the non-volatile memory.

Reset delay circuit for an electronic postage meter

A circuit for selecting one of a plurality of positive voltages when both can be applied to an integrated circuit. The circuit comprises a sensing apparatus for determining which of the plurality of voltages is the highest, apparatus for providing the highest voltage to the substrate and apparatus for applying the highest of the plurality of voltages to the substrate to insure protection and proper operation of the integrated circuit.

Integrated circuit substrate bias selection circuit

A mode detection circuit is disclosed that provides a high or low digital output signal to an associated circuit analog dependent upon the corresponding input signal. The input signal to the mode detection circuit will determine whether the mode of the input signal and associated circuit is to be external or internal. In this embodiment, the input of the mode detection circuit receives either a first voltage in the internal or a second voltage in the external mode which is lower than the first voltage. Thus, when the input voltage to the circuit is the first voltage, there is provided at the output a digital output that is high. In this embodiment, a high digital output signal would mean that the associated circuit with the detection circuit would be in the internal mode. On the other hand, when the analog input signal is the second voltage, there would be provided at the output of the detection circuit a low digital output signal which would mean that the associated circuit would be in the external mode. Accordingly, this circuit utilizes digital detect logic to which network (i.e. external or internal) of the associated circuit is to be utilized depending upon the voltage level which is provided at the input of the mode detection circuit.

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Lake Carmel, NY, United States of America

Warren G Hafner