International Business Machines Corporation

Other

Globalfoundries Inc.

Warren Edward Maule

Kevin Charles Gower

Kyu-hyoun Kim

Charles Arthur Kilmer

Hillery C Hunter

Paul William Coteus

Mark Andrew Brittain

Ravi Kumar Arimilli

Robert Brett Tremaine

John Michael Kaiser

Stephen P Glancy

Marc Avery Gollub

Michael B Healy

Kevin M Mcilvain

Luis Alfonso Lastras-Montano

Saravanan Sethuraman

Timothy Jay Dell

Gary A Van Huben

Edgar Rolando Cordero

Sanjeev Ghai

Mark William Kellogg

Brad William Michael

John Steven Dodson

Patrick James Meaney

Kenneth Lee Wright

Jeffrey A Stuecheli

Daniel Mark Dreps

David D Cadigan

John Stanley Bialas, Jr

Jerry Don Lewis

James Stephen Fields, Jr

Lakshminarayana Baba Arimilli

Diyanesh B Chinnakkonda Vidyapoornachary

James A O'Connor

Eric Eugene Retter

Barry Marshall Trager

Adam J McPadden

Kevin W Kark

David Wayne Victor

Brian John Connolly

Kyu-Hyoun Kim

Steven R Carlough

John Kenneth DeBrosse

Stephen J Powell

Anuwat Saetow

Michael Raymond Trombley

Jie Zheng

Joab Daniel Henderson

George L Chiu

Susan M Eickhoff

Thomas Basil Smith, Iii

Gary Alan Morrison

Rona Yaari

Kirk David Peterson

Ashish Jagmohan

Todd Edward Takken

Michele M Franceschini

Scott Barnett Swaney

Anil Bindu Lingambudi

Shmuel Winograd

Sridhar H Rangarajan

John B DeForge

Vicente Enrique Chung

Luiz Carlos Alves

Robert Dominick Mirabella

Juergen Saalmueller

Lucas W Mulkey

William John Starke

Toshiaki Kirihata

Karthick Rajamani

Frank David Ferraiolo

Naresh Nayar

William Paul Hovis

Richard Loise Arndt

Edward Joseph Seminaro

Darren Lane Anand

Shawn Anthony Hall

Peter Joseph Heyrman

Douglas James Joseph

Andrew Henry Wottreng

Tony Emile Sawan

Edward Hugh Welbon

Alphonso Philip Lanzetta

Richard Nicholas

Jeffrey H Dreibelbis

Harry R Bickford

Dustin James VanStee

Steven William Tomashot

George William Daly, Jr

Roy Stuart Moore

Thomas James Osten

Irving G Baysah

Raymond J Eberhard

Diyanesh Babu C Vidyapoornachary

Daniel James Henderson

Vincent P Zeyak, Jr

David A Larson Stanton

Diyanesh B C Vidyapoornachary

James D Wagoner

Randall Scott Jensen

A memory system for storing data is disclosed, the memory system including a plurality of memory devices configured to store data, each memory device having a plurality of bits, the memory devices configured and associated to work together as a rank to respond to a request; a memory control circuit associated with the plurality of memory devices and configured to output command and control signals to the plurality of memory devices; a detector for detecting a bit error in an operation; and a controller for remapping the bit error to a spare bit lane in response to the detector detecting the bit error.

Efficient and selective sparing of bits in memory systems

A method and/or system for checking the bus/interface between a host and a memory system during memory access operations includes a memory system having one or more of the data memory devices and a spare memory device; providing a bus/interface between a host and the memory system; selecting information on a per memory device basis to associate with a spare memory device; disassociating the selected information from the one or more data memory devices and associating the selected information with the spare memory device; adding Cyclical Redundancy Check (CRC) code to the one or more data memory devices from which the selected information was disassociated; transferring the CRC code and information over the bus and interface between the host and the memory system; and checking the bus interface with the CRC code added to the one or more data memory devices.

Method and apparatus to reduce bandwidth overhead of CRC protection on a memory channel

One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communication links. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. The memory system, architectural structure and/or method improves the ability of the communications links to transfer data downstream to the data buffer circuits. The memory control circuit receives a store command and a store data tag (Host tag) from a Host and sends the store data command and the store data tag to the data buffer circuits. No store data tag or control signal is sent over the communication links between the Host and the data buffer circuits, only data is sent over the communication links between the Host and the data buffer circuits.

Address/command chip controlled data chip address sequencing for a distributed memory buffer system

In an approach a request to write data to memory is received, wherein the memory includes: a first set of dynamic random-access memory (DRAM) accessible via a first memory channel, and a first set of storage class (SCM) memory accessible via a second memory channel. The data is written to the first set of DRAM via the first memory channel. The data is mirrored to the first set of SCM via the second memory channel.

Hybrid memory mirroring using storage class memory

A memory subsystem is disclosed comprising at least one memory module, the memory module having a substrate to which a plurality of memory chips is mounted and a voltage regulator, the voltage regulator receiving a power supply signal from a system power supply and outputting two or more power signals, each power signal providing a different, regulated voltage, which regulated voltages are each routed to each of the memory chips; and a redundant voltage regulator external to and not mounted on the memory module and configured to output two or more power signals, providing external different, regulated voltages which are the same voltages as the voltages output by the voltage regulator on the memory module, and supplying the two or more signals to the memory module.

Redundant voltage regulator for memory devices

A technique relates to operating a memory controller. The memory controller drives first memory devices and second memory devices of the memory controller in a dual channel mode. A first error correcting code (ECC) memory device and a second ECC memory device protect the first memory devices and the second memory devices. The memory controller drives the first memory devices and the second memory devices in a single channel mode such that the second ECC memory device is a spare memory device, and the first ECC memory device protects the first memory devices and the second memory devices. The memory controller is configured to switch between the dual channel mode and the single channel mode.

Using dual channel memory as single channel memory with spares

Tracking address ranges for computer memory errors including detecting, by memory logic, an error at a memory address, the memory address representing one or more memory cells at a physical location of computer memory; reporting, by the memory logic to memory firmware, the detected error including providing the memory firmware with the memory address; identifying, by the memory firmware, an address range affected by the detected error including scanning the computer memory in dependence upon the memory address; determining, by the memory firmware, a region size based on the address range affected by the detected error; and populating an entry in a mark table corresponding to the detected error, including populating a field specifying the region size and a field specifying a match address corresponding to the memory address.

Tracking address ranges for computer memory errors

Performing error correction in computer memory including receiving a read request targeting a read address within the computer memory; accessing a mark table comprising a plurality of entries, each entry including a field specifying a region size, a field specifying a match address, and a field specifying a mark location; performing a lookup of the mark table using the read address including, for each entry in the mark table: generating a mask based on the region size stored in the entry; determining, based on the mask, whether the read address is within a memory region specified by the match address and region size stored in the entry; and if the read address is within the memory region specified by the match address and region size stored in the entry, performing error correction using the mark location stored in the entry.

Performing error correction in computer memory

Embodiments of the present invention include a memory module that includes a plurality of memory devices and a memory buffer device. The memory devices are characterized as one of a high or low random bit error rate (RBER) memory device. The memory buffer device includes a read data interface to receive data read from a memory address on one of the memory devices, and common error correction logic to detect and correct error conditions in data read from both high RBER and low RBER memory devices. The memory buffer device also includes refresh rate logic configured to adjust a refresh rate based on the detected error conditions.

Common high and low random bit error correction logic

Embodiments of the present invention include a memory module that includes a plurality of memory devices and a memory buffer device. Each of the memory devices are characterized as one of a high random bit error rate (RBER) and a low RBER memory device. The memory buffer device includes a read data interface to receive data read from a memory address on one of the memory devices. The memory buffer device also includes common error correction logic to detect and correct error conditions in data read from both high RBER and low RBER memory devices. The common error correction logic includes a plurality of error correction units which provide different complexity levels of error correction and have different latencies. The error correction units include a first fast path error correction unit for isolating and correcting random symbol errors.

One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communication links. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. In one aspect, the data buffer circuit receives a next to be used store data tag from a Host wherein the store data tag specifies the data buffer location in the data buffer circuit to store data, and in response to receiving store data from the Host, moves the data received at the data buffer circuit into the data buffer pointed to by the previously received store data tag.

Host controlled data chip address sequencing for a distributed memory buffer system

Growing community of inventors

Cedar Park, TX, United States of America

Warren Edward Maule