International Business Machines Corporation

Warren E Price

Kenneth Allen Uplinger

Louis Bennie Capps, Jr

Vinod Kamath

Karl Klaus Dittus

Michael Sven Miller

Ralph M Begun

Raymond Mathew Clemo

Philip E Milling

Jimmy G Foster

Whitcomb Randolph Scott, Iii

Robert W Rupe

A system comprising a chassis that includes a plurality of modules and a fan assembly disposed in a distal end of the chassis for drawing air in parallel pathways through the plurality of modules. At least one of the modules is a compute module having a thermal sensor disposed to sense the temperature of air flowing across a processor mounted on a motherboard. The system further comprises a fan controller receiving output from the thermal sensor, wherein the fan controller operates the fan assembly to cool the plurality of modules and maintain the thermal sensor output within an operating temperature range. The fan controller controls the fan speed according to predetermined thermal profile settings associated with one of the compute modules received in the chassis. For example, the predetermined thermal profile settings may include a minimum fan speed, a maximum fan speed, and control loop feedback settings.

Plurality of configurable independent compute nodes sharing a fan assembly

A cache of a CPU/cache chip set, has a wide data path that is directly coupled, to a memory data bus having a narrow data path. The coupling is effected by a data transfer path comprising only conductors without any additional components that would introduce signal propagation delays. Cache data transfers are initiated by a cache controller. A bus controller provides data transfer control signals to transfer sets of data where each set has the same number of bits as the width of the memory bus. Data is transferred in burst cycles comprising a plurality of cache data transfer cycles. Each of the latter cycles comprises a plurality of memory bus cycles.

Data processing system with microprocessor/cache chip set directly

Data transfer between subsystems of an information handling system employing a multiple subsystem clock environment architecture, or between multiple information handling systems operating with different clock frequencies, is synchronized using a timing aligned multiple frequency synthesizer with a synchronization window decoder. A frequency generation circuit in circuit communication with a data synchronization circuit functions to produce a synchronized timing signal(s) to permit a central processing unit operating in one subsystem clock environment to function with a peripheral subsystem(s), such as a memory controller, operating in a different subsystem clock environment, or permits information handling systems operating with different clock frequencies to function with one another. Data transfer synchronization delays are reduced and mean-time-to-failure of signal synchronization accuracy is increased by eliminating metastability effects from the synchronization circuitry.

Method and apparatus for phase-aligned multiple frequency synthesizer

A logic circuit mechanism for inducing a processing unit to release a LOCK signal that the processing unit uses to secure continuous access to a memory system during read modify write operations requiring 'atomic' (continuous) access. The processing unit has an internal cache enabling it to set up consecutive memory access operations at a pace such that the LOCK signal could be held continuously active while a string of atomic memory accesses is carried out. The present circuit mechanism prevents premature release of the processing unit's LOCK signal, by asserting a Hold signal which requires the processing unit to release its LOCK signal but only after that unit has fully completed its current atomic access operation. The logic circuit reduces its impact on processing unit performance by detecting when the LOCK signal has been active continuously for N consecutive atomic operations coinciding with external contention, and calling for release of the CPUs LOCK signal only while the Nth such operation is being conducted.

Mechanism for efficiently releasing memory lock, after allowing

A personal computer has two memory banks respectively connected to two parity check units operative to detect parity errors. Upon doing so, each unit feeds a parity error signal to a separate latch. The latches are connected to a logic circuit which is in turn connected to an interrupt controller that initiates an interrupt when a parity error occurs. One latch is further connected to a check bit of a register of an I/O port and the check bit is set by the one latch. An interrupt handler reads the register and provides messages indicating which memory bank caused the parity error.

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Boca Raton, FL, United States of America

Warren E Price