Intel Corporation

Intel Corporatoin

Warren E Ferguson

Thomas D Fletcher

Dennis Ryan Bradford

Robert Valentine

Mark Jay Charney

Jesus Corbal

Edward Thomas Grochowski

Milind Baburao Girkar

Roman S Dubtsov

Nikita A Shustrov

Ping Tak Tang

Brian J Hickmann

Jesus Corbal San Adrian

Taraneh Bahrami

Robert N Hanek

Avi A Tevet

Michael Ferry

Jingwei Zhang

Embodiments of systems, apparatuses, and methods for chained fused multiply add. In some embodiments, an apparatus includes a decoder to decode a single instruction having an opcode, a destination field representing a destination operand, a first source field representing a plurality of packed data source operands of a first type that have packed data elements of a first size, a second source field representing a plurality of packed data source operands that have packed data elements of a second size, and a field for a memory location that stores a scalar value. A register file having a plurality of packed data registers includes registers for the plurality of packed data source operands that have packed data elements of a first size, the source operands that have packed data elements of a second size, and the destination operand. Execution circuitry executes the decoded single instruction to perform iterations of packed fused multiply accumulate operations by multiplying packed data elements of the sources of the first type by sub-elements of the scalar value, and adding results of these multiplications to an initial value in a first iteration and a result from a previous iteration in subsequent iterations.

Systems, apparatuses, and methods for chained fused multiply add

An apparatus and method for performing a check on inputs to a mathematical instruction and selecting a default sequence efficiently managing the architectural state of a processor. For example, one embodiment of a processor comprises: an arithmetic logic unit (ALU) to perform a plurality of mathematical operations using one or more source operands; instruction check logic to evaluate the source operands for a current mathematical instruction and to determine, based on the evaluation, whether to execute a default sequence of operations including executing the current mathematical instruction by the ALU or to jump to an alternate sequence of operations adapted to provide a result for the mathematical instruction having particular types of source operands more efficiently than the default sequence of operations.

Apparatus and method for performing a check to optimize instruction flow

A mechanism for performing single-path floating-point rounding in a floating point unit is disclosed. A system of the disclosure includes a memory and a processing device communicably coupled to the memory. In one embodiment, the processing device comprises a floating point unit (FPU) to generate a plurality of status flags for a rounded value of a finite nonzero number. The plurality of status flags are generated based on the finite nonzero number without calculating the rounded value of the finite nonzero number. The plurality of status flags comprises an overflow flag and an underflow flag. The FPU determines whether a rounded value should be calculated for the finite nonzero number based on the plurality of status flags and whether the overflow flag is asserted. Upon determining that the rounded value should be calculated for the finite nonzero number based on the plurality of status flags and that the overflow flag is asserted, the FPU calculates the rounded value of the finite nonzero number based on an overflow rounding. Upon determining that the rounded value should be calculated for the finite nonzero number based on the plurality of status flags and that the overflow flag is not asserted, the FPU calculates the rounded value of the finite nonzero number based on a blended reduced precision rounding.

Method, apparatus, system for single-path floating-point rounding flow that supports generation of normals/denormals and associated status flags

Methods, machines, and systems are provided for very high radix division using narrow data paths. A numerator and denominator are received for a very high radix division calculation. An approximate reciprocal of the denominator is obtained from a data structure. The numerator and denominator are pre-scaled by the reciprocal. The denominator is decomposed to an equivalent expression that results in a number of leading insignificant values. Next, modifying a current remainder by forming a first product and subtracting the equivalent expression iteratively assembles a quotient.

Narrow data path for very high radix division

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Beaverton, OR, United States of America

Warren E Ferguson