International Business Machines Corporation

Warren D Dyckman

Edward R Pillai

Michael Jay Shapiro

Louis Bennie Capps, Jr

Michael Richard Ouellette

Anand Haridass

Jeffrey Allen Zitz

Daniel P O'Connor

James Douglas Jordan

Ronald Edward Newhart

Gary Lafontant

Deana Cosmadelis

Joanne Ferris

A design structure for a processor may be embodied in a machine readable medium for designing, manufacturing or testing a processor integrated circuit. The design structure may control heat generation in a multi-core processor. The design structure may specify that each processor core includes a temperature sensor that reports temperature information to a processor controller. The design structure may also specify that if a particular processor core exceeds a predetermined temperature, the processor controller disables that processor core to allow that processor core to cool. The design structure may also specify that the processor controller enables the previously disabled processor core when the previously disabled processor core cools sufficiently to a normal operating temperature. In this manner, a multi-core processor may avoid undesirable hot spots that impact processor life.

Structure for an apparatus for monitoring and controlling heat generation in a multi-core processor

A system and method to optimize multi-core microprocessor performance using voltage offsets is presented. A multi-core device tests each of its processor cores in order to identify each processor core's optimum supply voltage. In turn, the device configures voltage offset networks for each processor core based upon each processor core's identified optimum supply voltage. As a result, the offset voltages produced by the voltage offset networks are subtracted from the multi-core device's main voltage, which results in the voltage offset networks supplying optimum supply voltages to each processor core. The voltage offset networks may include fuses to generate a fixed voltage offset, or the voltage offset networks may include a control circuit to dynamically adjust voltage offsets during the multi-core device's operation.

System and method to optimize multi-core microprocessor performance using voltage offsets

The disclosed methodology and apparatus may reduce heat generation in a multi-core processor. In one embodiment, a multi-core processor cycles selected processor cores off in a predetermined pattern across the processor die over time to reduce the average heat generation by the processor. The disclosed multi-core processor may reduce or avoid undesirable hot spots that impact processor life.

Method and apparatus for controlling heat generation in a multi-core processor

The disclosed methodology and apparatus may control heat generation in a multi-core processor. In one embodiment, each processor core includes a temperature sensor that reports temperature information to a processor controller. If a particular processor core exceeds a predetermined temperature, the processor core disables that processor core to allow it to cool. The processor core enables the previously disabled processor when the previously disabled processor core cools sufficiently to a normal operating temperature. The disclosed multi-core processor may avoid undesirable hot spots that impact processor life.

Method and apparatus for monitoring and controlling heat generation in a multi-core processor

The present invention provides a technique for adjusting the size of clearance holes for impedance control in multilayer electronic packaging and printed circuit boards. The method comprises: providing parameters for a structure having a clearance hole and at least one via passing through the clearance hole; calculating a characteristic impedance for the at least one via; and adjusting at least a size of the clearance hole until the characteristic impedance for the at least one via is approximately equal to a desired characteristic impedance.

Clearance hole size adjustment for impedance control in multilayer electronic packaging and printed circuit boards

Disclosed is a method and structure for locally powering a semiconductor chip within a package. The structure and method incorporate a local voltage regulator mounted adjacent a semiconductor chip on a top surface of a carrier. The voltage regulator is electrically connected to a power plane disposed within the carrier. The voltage regulator continuously senses the reflected voltage of the power plane at a regulated output port and actively cancels time domain noise within its operational bandwidth. Mounting the voltage regulator on top of the carrier adjacent to the chip minimizes loop inductance between the regulator and power plane and also minimizes delay caused by impedance of the power plane on the current flowing to the chip.

In-module current source

In packaging integrated circuits for high speed (multi-gigabit) applications, chip carriers having signal paths between the substrate board and the chips at the top with a number of evenly divided vertical steps produces frequency properties that are sufficiently good that it is possible to run signals through the package, rather than by means of connectors attached to the top surface of the carrier.

Multi-step transmission line for multilayer packaging

A high power density thermal packaging solution. A highly efficient thermal path is provided using a lid of a unique design configuration that connects the chip back-side to both a heat sink and thermally conductive substrate vias thus establishing two thermal paths to carry heat from the die. The thermal interface between the chip back-side to lid and lid-to-substrate is enhanced with a thermally conductive elastomer. The heat is conducted through the substrate through thermal vias that are added to the perimeter of the substrate or which may be configured from preexisting electrical shielding structures that connect the top surface of the substrate to the bottom of the package. The bottom surface connection then conducts the heat to a copper ground plane in the printed circuit card. The heat from the die to the heat sink is transferred in the conventional method using the thin layer of thermally conductive elastomer to complete the thermal path from chip to lid to heat sink.

High density thermal solution for direct attach modules

In a package for integrated circuits, a signal transmission line has a first segment closer to the chip that is bracketed vertically by ground planes at a first vertical distance and a second segment further from the chip that is bracketed vertically by ground planes at a second vertical distance greater than the first distance, with an aperture being formed in the ground planes at the first distance, so that those ground planes do not interfere with the impedance set by the second set of ground planes.

Growing community of inventors

Peekskill, NY, United States of America

Warren D Dyckman