Ovonyx Inc.

Sandisk Technologies Inc.

Micron Technology Incorporated

Western Digital Technologies, Inc.

Avx Corporation

Hgst, Inc.

Other

Intel Corporation

Stmicroelectronics S.r.l.

Ovonyx Memory Technology, LLC

Carlow Innovations LLC

Stmicroelectroncis S.r.l.

Ward M Parkinson

James E O'Toole

Nathan Franklin

Thomas Michael Trent

Michael Grobis

Michael Nicolas Albert Tran

Tyler A Lowrey

Daniel Robert Shepard

Guy Charles Wicker

Stephen L Casper

Raj K Ramanujan

Ilya V Karpov

Yukio Fuji

Elliott Philofsky

Dennis Wilson

Christopher John Petti

Neil Leslie Robertson

Martin Aureliano Hassner

Won Ho Choi

Martin Lueker-Boden

Sergey A Kostylev

Gianpaolo Spadini

Semyon D Savransky

George A Gordon

James Reed

Kevin G Duesman

Zvonimir Z Bandic

Dimitri Houssameddine

Wen-Foo Chern

Sean Jong Lee

John M Peters

Thomas M Trent

Hans Jurgen Richter

Stefan K Lai

Zhaoqiang Bai

James W Reiner

Sam Ira Young

Steven Jeffrey Grossman

R Jacob Baker

Technology is disclosed for a current source for reading a memory cell having a threshold switching selector. The current source may be operated in a first mode when turning on the threshold switching selector and in a second mode when sensing a voltage across the memory cell. The first mode may allow the use of the full range of the power supply voltage, which provides sufficient voltage across the memory cell to turn on the threshold switching selector. In the second mode the magnitude of the read current is less dependent on the voltage across the memory cell. The second mode therefore provides for accurate sensing of the memory cell. The first mode may also be used when writing the memory cell, which provides sufficient voltage across the memory cell to write the memory cell.

Current source for read of programmable resistance memory cells

Technology is disclosed herein for reading programmable resistance memory cells. A first (faster) self-referenced read (SRR) of a group of memory cells is performed and if successful the read is complete. However, if the first SRR fails then a second (slower or nominal) SRR is performed. The bit error rate (BER) of the second SRR may be significantly lower than the BER of the first SRR. However, the BER of the first SRR may be low enough such that most of the time the first SRR is successful. Therefore, most of the time the read is completed with just the first SRR, thereby providing for an SRR having on average is faster than if just the second SRR had been used. Moreover, the effective BER of the SRR is extremely low due to the low BER of the second SRR.

Fast self-referenced read of programmable resistance memory cells

Technology is disclosed herein for refreshing threshold switching selectors in programmable resistance memory cells in cross-point memory arrays. The Vt of the threshold switching selector may drift over time. The memory system resets the Vt of the threshold switching selectors with a selector refresh operation and uses a separate data refresh operation to refresh data in programmable resistance memory elements. The data refresh operation itself may also refresh the selector. However, the threshold switching selector refresh operation is faster than the data refresh operation. Moreover, the selector refresh operation consumes much less power and/or current then the data refresh operation. The selector refresh operation may thus be performed at a higher rate than the data refresh operation.

Cross-point array refresh scheme

Concurrent access of multiple memory cells in a cross-point memory array is disclosed. In one aspect, a forced current approach is used in which, while a select voltage is applied to a selected bit line, an access current is driven separately through each selected word line to concurrently drive the access current separately through each selected memory cell. Hence, multiple memory cells are concurrently accessed. In some aspects, the memory cells are accessed using a self-referenced read (SRR), which improves read margin. Concurrently accessing more than one memory cell in a cross-point memory array improves bandwidth. Moreover, such concurrent accessing allows the memory system to be constructed with fewer, but larger cross-point arrays, which increases array efficiency. Moreover, concurrent access as disclosed herein is compatible with memory cells such as MRAM which require bipolar operation.

Concurrent multi-bit self-referenced read of programmable resistance memory cells in cross-point array

Concurrent write to programmable resistance memory cells in cross-point array

Technology for read in a cross-point memory array. Drive transistors pass read and write currents to the cross-point memory array. The read current charges a selected word line to turn on a threshold switching selector of a selected memory cell. While the threshold switching selector is on, the current (read or write) passes through the selected memory cell. The memory system applies a smaller overdrive voltage to a drive transistor when the drive transistor is passing the read current than when the drive transistor is passing the write current. A smaller overdrive voltage increases the resistance of the drive transistor. Increasing the resistance of the drive transistor increases the resistance seen by the threshold switching selector in the selected memory cell, which reduces the Ihold of the threshold switching selector.

Cross-point array IHOLD read margin improvement

Technology for reading reversible resistivity cells in a memory array when using a current-force read is disclosed. The memory cells are first read using a current-force referenced read. If the current-force referenced read is successful, then results of the current-force referenced read are returned. If the current-force referenced read is unsuccessful, then a current-force self-referenced read (SRR) is performed and results of the current-force SRR are returned. In an aspect this mixed current-force read is used for MRAM cells, which are especially challenging to read.

Mixed current-forced read scheme for MRAM array with selector

A circuit is provided that includes a first transistor having a first terminal, a second terminal and a third terminal, and a second transistor comprising a first terminal, a second terminal and a third terminal. The first terminal of the first transistor comprises an input terminal of the circuit, the second terminal of the first transistor is coupled to a power supply bus, and the first transistor conducts a first current. The first terminal of the first transistor comprises an output terminal of the circuit, the second terminal of the second transistor is coupled to the power supply bus, and the third terminal of the second transistor is coupled to the third terminal of the first transistor. The second transistor conducts a second current proportional to the first current substantially independent of distance between the first transistor and the second transistor.

Current mirror circuits

Technology is disclosed for a fast ECC engine for a mixed read of MRAM cells. A codeword read from MRAM cells using a referenced read is decoded using a first ECC mode. If decoding passes, results are provided to a host. If decoding fails, a self-referenced read (SRR) is performed. The data read using the SRR is decoded with a second ECC mode that is capable of correcting a greater number of bits than the first ECC mode. The second ECC mode may have a higher mis-correction rate than the first ECC mode (for a given raw bit error rate (RBER)). However, the RBER may be lower when using the second ECC mode. Therefore, the first and second ECC modes may result in about the same probability of an undetectable error (or mis-correction).

Programmable ECC for MRAM mixed-read scheme

A control circuit is configured to connect to a cross-point memory array in which each conductive line, such as a bit line or word line, is connected to a transistor pair comprising a pMOSFET in parallel with an nMOSFET. When selecting a memory cell to be read, a voltage of a first conductive line may be pulled up using the pMOSFET in a conductive state while the nMOSFET is in a non-conductive state. Further, when reading the selected memory cell, the parallel nMOSFET of the first conductive line may be in a conductive state.

Signal amplification in MRAM during reading, including a pair of complementary transistors connected to an array line

In a memory array with a cross-point structure, at each cross-point junction a programmable resistive memory element, such as an MRAM memory cell, is connected in series with a threshold switching selector, such as an ovonic threshold switch. The threshold switching selector switches to a conducting state when a voltage above a threshold voltage is applied. When powered down for extended periods, the threshold voltage can drift upward. If the drift is excessive, this can make the memory cell difficult to access and can disturb stored data values when accessed. Techniques are presented to determine whether excessive voltage threshold drift may have occurred, including a read based test and a time based test.

Power off recovery in cross-point memory with threshold switching selectors

Technology for limiting a voltage difference between two selected conductive lines in a cross-point array when using a forced current approach is disclosed. In one aspect, the selected word line voltage is clamped to a voltage limit while driving an access current through a region of the selected word line and through a region of the selected bit line. The access current flows through the memory cell to allow a sufficient voltage to successfully read or write the memory cell, while not placing undue stress on the memory cell. In some aspects, the maximum voltage that is permitted on the selected word line depends on the location of the selected memory cell in the cross-point memory array. This allows memory cells for which there is a larger IR drop to receive an adequate voltage, while not over-stressing memory cells for which there is a smaller IR drop.

Forced current access with voltage clamping in cross-point array

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Boise, ID, United States of America

Ward M Parkinson