Ovonyx Inc.

Micron Technology Incorporated

Intel Corporation

Ovonyx Memory Technology, LLC

Mostek Corporation

Carlow Innovations LLC

Ovoynx, Inc.

Ward D Parkinson

Tyler A Lowrey

Wen-Foo Chern

Thomas M Trent

Ferdinando Bedeschi

Ilya V Karpov

Roberto Gastaldi

Claudio Resta

George A Gordon

Kevin G Duesman

Sergey A Kostylev

Gary M Johnson

Giulio Casagrande

Semyon D Savransky

Gianpaolo Spadini

James Reed

Leland R Nevill

Stanley N Protigal

Zhitong Chen

Stanford R Ovshinsky

Charles C Kuo

Mirmajid Seyyedy

Guy Charles Wicker

William K Waller

John M Peters

Charles H Dennison

Stephen L Casper

Eugene H Cloud

Stephen J Hudgens

Paul S Zagar

Wolodymyr Czubatyj

Timothy J Allen

Randal W Chance

Manzur Gill

Jeffrey S Mailloux

Joseph B Wicklund

Edward J Heitzeberg

Douglas M Kelly

Web-Foo Chern

Allen Benn

Disturb from the reset to the set state may be reduced by creating an amorphous phase that is substantially free of crystal nuclei when programming the reset state in a phase change memory. In some embodiments, this can be achieved by using a current or a voltage to program that exceeds the threshold voltage of the phase change memory element, but does not exceed a safe current voltage which would cause a disturb.

Immunity of phase change material to disturb in the amorphous phase

A seasoned phase change memory has been subjected to a longer pulse to adjust resistance levels prior to use of the phase change memory.

Seasoning phase change memories

A voltage derived from accessing a selected bit using one read current may be utilized to read a selected bit of an untriggered phase change memory after the read current is changed. As a result, different reference voltages may be used to sense the state of more resistive versus a less resistive selected cells. The resulting read window or margin may be improved in some embodiments.

Method for using a bit specific reference level to read a phase change memory

A phase change memory may be utilized in place of more conventional, higher volume memories such as static random access memory, flash memory, or dynamic random access memory. To account for the fact that the phase change memory is not yet a high volume technology, an error correcting code may be incorporated. The error correcting code may be utilized in ways which do not severely negatively impact read access times, in some embodiments.

Using a phase change memory as a high volume memory

A phase change memory cell may be read by driving a current through the cell higher than its threshold current. A voltage derived from the selected column may be utilized to read a selected bit of a phase change memory. The read window or margin may be improved in some embodiments. A refresh cycle may be included at periodic intervals.

Reading a phase change memory

Using a bit specific reference level to read a memory

Using a shorter read pulse width may increase read window in some embodiments. This may allow the use of higher voltages with less likelihood of a read disturb where a bit unintentionally changes phase.

Read window in chalcogenide semiconductor memories

Using a bit specific reference level to read a resistive memory

A read current high enough to threshold a phase change memory element may be used to read the element without thresholding the memory element. The higher current may improve performance in some cases. The memory element does not threshold because the element is read and the current stopped prior to triggering the memory element.

Reading phase change memories

Using higher current to read a triggered phase change memory

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Boise, ID, United States of America

Ward D Parkinson