Data General Corporation

Ward Baxter, Ii

Thomas M Jones

Ronald H Gruner

Brett L Bachman

Michael B Druke

David L Houseman

Steven M Haeffele

William N Coder

Stephen R Redfield

Michael L Ziegler

Craig J Mundie

Gerald F Clancy

Charles J Young

John R Van Roekel

Louis E Drew

A digital data system having a memory with a unique multi-ported memory I/O means. Separate means are provided for communicating with any of several buses. Address information, operands, instructions and Input/Output data may be separately sent and received over various of the buses.

Unique memory for use in a digital data system

A data processing system having a flexible internal structure, protected from and effecitvely invisible to users, with multilevel control and stack mechanisms and capability of performing multiple, concurrent operations, and providing a flexible, simplified interface to users. The system is internally comprised of a plurality of separate, independent processors, each having a separate microinstruction control and at least one separate, independent port to a central communications and memory node. The communications and memory node is an independent processor having separate, independent microinstruction control and comprised of a plurality of independently operating, microinstruction controlled processors capable of performing multiple, concurrent memory and communications operations. Addressing mechanisms allow permanent, unique identification of information and an extremely large address space accessible and common to all such systems. Addresses are independent of system physical configuration. Information is identified to bit granular level and to information type and format. Protection mechanisms provide variable access rights associated with individual bodies of information. User language instructions are transformed into dialect coded, uniform, intermediate level instructions to provide equal facility of execution for all user languages. Operands are referred to by uniform format names which are transformed, by internal mechanisms transparent to users, into addresses.

Digital data processing system

A data processing system having a flexible internal structure, protected from and effectively invisible to users, with multilevel control and stack mechanisms and capability of performing multiple, concurrent operations, and providing a flexible, simplified interface to users. The system is internally comprised of a plurality of separate, independent processors, each having a separate microinstruction control and at least one separate, independent port to a central communications and memory node. The communications and memory node is an independent processor having separate, independent microinstruction control and comprised of a plurality of independently operating, microinstruction controlled processors capable of performing multiple, concurrent memory and communications operations. Addressing mechanisms allow permanent, unique indentification of information as objects and an extremely large address space accessible and common to all such systems. Addresses are independent of system physical configuration. Information is identified to bit granular level and to information type and format. Protection mechanisms provide variable access rights associated with individual bodies of information. User language instructions are transformed into dialect coded, uniform, intermediate level instructions to provide equal facility of execution for all user languages. Operands are referred to by uniform format names which are transformed, by internal mechanisms transparent to users, into addresses.

Digital data processing system having an I/O means using unique address

A data processing system in which the bits of each stored word in a memory thereof are refreshed periodically. At substantially the same time the refresh operation with respect to each word occurs, an error detection operation also occurs and, if an error is detected in a word that is being refreshed, the error is then corrected and the corrected word is written back into the memory. Thus, errors are continuously being checked with no more use of machine time then is required for the refresh operation. Error correction, when necessary, then takes place at a fixed frequency, a limit thereby being placed on the error correction process. If errors in a work are detected when the word is requested for access by a requestor, the error is corrected before the word is supplied to the requestor but the corrected word is not written back into memory at that time, the word in memory being again detected and corrected at its next refresh operation.

Refresh and error detection and correction technique for a data

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Carlisle, MA, United States of America

Ward Baxter, Ii