Samsung Electronics Co., Ltd.

Wansoo Choi

Dongeun Shin

Youngwook Kim

Heehyun Nam

Sumin Ahn

Heeyeon Tak

Hyunseon Park

Dohyeon Park

A memory system includes a memory device including a memory cell array, a first latch, a plurality of program latches, and a second latch and a memory controller configured to provide a command to the memory device. The memory device may sense first data from a first region of the memory cell array, store the sensed first data in the first latch, transfer the sensed first data to the second latch, output the first data from the second latch to the memory controller, and transfer the first data from the second latch to a first program latch of the plurality of program latches, in response to a first read command.

Memory device, memory system including the same, and operating method of the memory system

A memory controller with improved data reliability and a memory system including the same are provided, and an operating method of the memory controller includes, based on deterioration information indicating a location of a deterioration region in the plurality of blocks, with respect to data stored in a first block, copying user data of a RAID to a normal region other than the deterioration region of a second block; copying parity data of the RAID among the data stored in the first block to the deterioration region of the second block; and updating mapping information between data constituting one RAID and transmitting the mapping information to the memory device. The deterioration information includes information regarding one or more word lines at specific locations included in the deterioration region in the plurality of blocks.

Memory controller with improved data reliability and memory system including the same

A storage device includes a memory device including a plurality of memory cells respectively storing data having a plurality of bits, and a memory controller including an operation block including a plurality of unit circuits executing a predetermined function, and a core block executing a control operation on the plurality of memory cells in response to a command from a host. The core block selects at least portions of the plurality of unit circuits to determine selection unit circuits, and generates a control command specifying an operation order of the selection unit circuits. In the operation block, the selection unit circuits operate by the operation order to determine a control voltage required for the control operation, and store the control voltage in at least one of the memory controller or the memory device.

Memory controller and storage device including the same

Growing community of inventors

Hwaseong-si, South Korea

Wansoo Choi