Micron Technology Incorporated

Wanmo Wong

Karunakaran Muthusamy

Brady L Keays

Roger Louie

Peter Sean Feeley

Theodore T Pekny

Frank J Sepulveda

Van Van Nguyen

John Sasinowski

Samuel A Shapero

Mark Jahn

Joseph Khatami

Christopher Joseph Bueb

Aravind Ramamoorthy

Karunakaran Muthasamy

A multi-interface memory can include a memory package that includes a memory device and host interfaces coupled to the memory device. Each of the host interfaces is configured to operate according to a different protocol. The memory package can be coupled to a host via one or more of the host interfaces. More than one of the host interfaces can share a contact.

Multi-interface memory

Various embodiments include methods, apparatus, and systems for assigning a plurality of version number values to instances of a logical entity of a memory device. Each version number value of the plurality version number values may be separately assigned to one of the instances of the logical entity. The version number values may be recycled after the plurality of version number values are assigned. Other embodiments including additional methods, apparatus, and systems are disclosed.

Recycled version number values in flash memory

Methods, systems, and devices for techniques for managed NAND translation with embedded memory systems are described. A host system may generate a first command to access a logical memory address associated with a memory system. The host system may identify a physical memory address of the memory system based on generating the first command. The host system may output to the memory system a second command and the physical memory address, where the second command may be communicated to the memory device using a protocol associated with a controller of the memory system. The memory system may then access memory cells in a memory device associated with the physical memory address based on receiving the second command and the physical memory address.

Techniques for managed NAND translation with embedded memory systems

Embodiments for partitioning a non-volatile memory device is described. In one embodiment a memory system includes a first addressable range of memory blocks for storing different types of data. The memory system is partitioned to include a second addressable range of memory blocks capable of storing data indicating attributes of the first addressable range of memory blocks. The second addressable range of memory blocks may also be periodically updated such that the capacities of the first addressable range of memory blocks may be dynamically adjusted depending on application needs and changes to the non-volatile memory device over time. In some embodiments, one partition of a memory device may be configured for high reliability data storage while a second partition is configured for normal reliability storage.

Method and apparatus for a volume management system in a non-volatile memory device

Embodiments for partitioning a non-volatile memory device is described. In one embodiment a memory system includes a first addressable range of memory blocks for storing different types of data. The memory system is partitioned to include a second addressable range of memory blocks capable of storing data indicating attributes of the first addressable range of memory blocks. The second addressable range of memory blocks may also be periodically updated such that the capacities of the first addressable range of memory blocks may be dynamically adjusted depending on application needs and changes to the non-volatile memory device over time In some embodiments, one partition of a memory device may be configured for high reliability data storage while a second partition is configured for normal reliability storage.

A single segment data structure and method for storing data objects employing a single segment data object having a header and a data record. The header includes a segment length field describing the length of memory reserved for the data record and the data record contains at least one data instance object. Each of the data instance objects has a data instance header and data field. The header includes a data instance state field and a data instance length field. The data instance length field contains data representing the length of the data instance data field allowing for variable length 'in place' updating. The data instance state field contains data representing an object state of the instance data. Only one of the data instance objects of the data record of the single segment data object has a valid object state. The state field facilitates a power loss recovery process.

Managing memory data recovery upon power loss

Methods of operating non-volatile memory devices including dividing the non-volatile memory device into a plurality of sequentially addressed clusters, wherein each cluster contains a plurality of sequentially addressed logical blocks, and where at least one cluster of the plurality of sequentially addressed clusters addresses a different number of sequentially addressed logical blocks than another one of the clusters of the plurality of sequentially addressed clusters.

Cluster based non-volatile memory translation layer

One or more techniques are provided for programming a flash memory device. In one embodiment, the memory device is programmed such that a data pattern written to a page in the memory device has encoded therein an expected count value corresponding to the number of times a first binary value occurs in the data pattern. The data pattern includes the program data and the expected count value, and is written to the page in a single operation. The expected count value may be stored in a count field in the management area of the page. During a page read operation, the expected count value is compared to the actual count of the number of bits having the first binary value in the data area of the page. If the expected count is equal to the actual count, then the program data is determined to be valid.

Method for detecting flash program failures

An improved non-volatile memory and logical block to physical block address translation method utilizing a cluster based addressing scheme is detailed. The translation of logical blocks/sectors to the physical blocks/sectors is necessary for a non-volatile memory to appear as a freely rewriteable device to a system or processor. Embodiments of the present invention utilize cluster based address translation to translate logical block addresses to physical block addresses, wherein each cluster contains a plurality of sequentially addressed logical blocks. This allows the use of a smaller RAM table for the address translation lookup and/or faster scanning of the memory device or memory subsystem for the matching cluster address. In one embodiment, a specially formatted cluster is utilized for frequently updated sectors/logical blocks, where the cluster stores a single logical block and a new sequential physical block of the cluster is written in turn with each update.

A non-volatile memory data address translation scheme is described that utilizes a hierarchal address translation system that is stored in the non-volatile memory itself. Embodiments of the present invention utilize a hierarchal address data and translation system wherein the address translation data entries are stored in one or more data structures/tables in the hierarchy, one or more of which can be updated in-place multiple times without having to overwrite data. This hierarchal address translation data structure and multiple update of data entries in the individual tables/data structures allow the hierarchal address translation data structure to be efficiently stored in a non-volatile memory array without markedly inducing write fatigue or adversely affecting the lifetime of the part. The hierarchal address translation of embodiments of the present invention also allow for an address translation layer that does not have to be resident in system RAM for operation.

Growing community of inventors

Menlo Park, CA, United States of America

Wanmo Wong