Altera Corporation

Wanli Chang

Richard G Cliff

Chiakang Sung

Joseph Huang

Cameron R McClintock

Gregory W Starr

Andy Louie Lee

Richard Yen-Hsiang Chang

John E Turner

Brian D Johnson

Chiao Kai Hwang

Mian Z Smith

Tim Tri Hoang

L Todd Cope

Richard Y Chang

Sergey Yuryevich Shumarayev

David Edward Jefferson

Bahram Ahanin

William W Leong

James A Watson

Kazi Asaduzzaman

Kang Wei Lai

Kang-Wei Lai

Christopher F Lane

Ninh D Ngo

Leon Zheng

Mario E Guzman

By Louis Leong, Legal Representative

William Leong, Deceased

Richard Chang

Enhanced passgate structures for use in low-voltage systems are presented in which the influence of Von the range of signals passed by single-transistor passgates is reduced. In one arrangement, the V-Vlimit for signals propagated through NMOS passgates is raised by applying a higher V; in another arrangement, the Vis lowered. The use of CMOS passgates in applications where single-transistor passgates have traditionally been used is also presented.

Passgate structures for use in low-voltage applications

A phase frequency detector compares a reference clock signal to a feedback clock signal to generate pulses in one or more output signals. The one or more output signals have a minimum pulse width. The phase frequency detector has a temperature sensing circuit. The phase frequency detector adjusts the minimum pulse width of the one or more output signals using the temperature sensing circuit to compensate for variations in the temperature of the phase frequency detector.

Phase frequency detectors generating minimum pulse widths

Techniques are provided for compensating for phase and timing delays in clock signals generated by phase-locked loops and delay-locked loops on integrated circuits. Circuit elements coupled in a feedback loop of a locked circuit can compensate for the timing and phase delays between an input pin and an output pin. Other circuit elements coupled in the feedback loop of a locked circuit can compensate for the delay between an input pin and a destination circuit element. Still other circuit elements coupled in an input reference path of a locked circuit preserve a timing relationship between input clock and input data signals. A clock signal and a data signal received at a destination circuit element have the same phase and timing relationship that exists between the input clock and input data signals at input pins.

Techniques for compensating delays in clock signals on integrated circuits

A feedback loop, such as a phase-locked loop, on an integrated circuit has a detector, a charge pump, and a loop filter. The charge pump adjusts its output current in response to variations in a process of the integrated circuit to reduce variations in the loop bandwidth. The charge pump also adjusts its output current in response to variations in a resistance of a resistor in the loop filter to reduce variations in the loop bandwidth. The charge pump can also adjust its output current in response to variations in a temperature of the integrated circuit to reduce variations in the loop bandwidth. A delay-locked loop on an integrated circuit has a phase detector and a charge pump. The charge pump adjusts its output current in response to variations in the temperature and the process of the integrated circuit to reduce changes in the loop bandwidth.

Loop circuits that reduce bandwidth variations

A sensing circuit senses the programmed state of fuses such as polysilicon (poly) fuses. In a preferred embodiment, the sensing circuit comprises first and second amplifier stages, a fuse and a reference resistor wherein the fuse and the reference resistor are connected, respectively, to first and second inputs of the first amplifier stage. The first and second amplifier stages are differential amplifiers and the output of the second amplifier stage is buffered. Circuitry for programming the fuse is part of the sensing circuit.

Fuse sensing circuit

A programmable logic device includes configurable phase-locked loop (PLL) circuitry that outputs multiple clock signals having programmable phases and frequencies. Each output signal is programmably selectable for use as an external clock, internal global clock, internal local clock, or combinations thereof. The PLL circuitry has programmable frequency dividing, including programmable cascaded frequency dividing, and programmable output signal multiplexing that provide a high degree of clock design flexibility.

Highly configurable PLL architecture for programmable logic

Enhanced passgate structures for use in low-voltage systems are presented in which the influence of Von the range of signals passed by single-transistor passgates is reduced. In one arrangement, the V&#x2212;Vlimit for signals propagated through NMOS passgates is raised by applying a higher V; in another arrangement, the Vis lowered. The use of CMOS passgates in applications where single-transistor passgates have traditionally been used is also presented.

Passage structures for use in low-voltage applications

A PLL circuit is described. The PLL circuit includes: a signal generator; and a spread spectrum modulator coupled to the signal generator, where the spread spectrum modulator receives a control voltage as an input and provides a spread spectrum control voltage to the signal generator in response to the control voltage. In one embodiment, the spread spectrum modulator includes at least one selector, where the at least one selector selects a plurality of voltage levels that correspond to a spread mode and percentage of spread for the spread spectrum modulator.

Analog implementation of spread spectrum frequency modulation in a programmable phase locked loop (PLL) system

A PLL circuit is described. The PLL circuit includes: a feedback loop and a loop filter coupled to the feedback loop, where the loop filter is programmable to provide one of a plurality of bandwidths. In one embodiment, the loop filter is programmable to provide one of a plurality of resistances, each resistance of the plurality of resistances corresponding to one of the plurality of bandwidths. In one embodiment, the feedback loop includes a detector and a signal generator coupled to the detector.

Programmable loop bandwidth in phase locked loop (PLL) circuit

At least some of the interconnection signaling on a programmable logic device ('PLD') is by differential signaling using differential driver circuitry to apply differential signals to a pair of conductors that extend to differential receiver circuitry. Such differential interconnection signaling helps the PLD operate satisfactorily with lower power supply voltages. The conductors in each differential signaling pair may cross over one another at various intervals in order to help reduce the adverse effects of capacitive coupling between adjacent and parallel signaling paths.

Differential interconnection circuits in programmable logic devices

A testing circuit and method for a phase-locked loop allow measurement of leakage currents in the phase-locked loop components. By forcing the output of the phase-frequency detector to a particular state, the charge pump can be disabled. This disables the effect of feedback in the phase-locked loop, and allowing the output frequency to be determined by the voltage on the control voltage node at the time the feedback is disabled. If there is no leakage, the control voltage, and therefore the output frequency, should remain the same as they were at the moment feedback was disabled. Monitoring the output frequency for changes provides an indication of the presence or absence of leakage. Conducting the test using two different charge pump reference currents allows one to detect leakage resulting from charge pump mismatch.

Testing circuit and method for phase-locked loop

A programmable variable depth and width random-access memory circuit is provided. The memory circuit contains rows and columns of memory cells for storing data. A row decoder is used to address individual rows of the memory cells. Column address circuitry receives a column address signal and a width and depth selection signal. A column decoder within the column address circuitry addresses one or more columns of memory cells of the RAM array based on the selected width of the array. The output of the column decoder is routed to the appropriate column or columns of memory cells by a pattern of fixed connections and a group of programmable multiplexers. The number of data output lines to which data signals are provided is determined by the selected width of the RAM array. The output circuitry contains a group of programmable demultiplexers and a routing array having a pattern of fixed connections suitable for passing data signals from the RAM array to the selected number of data output lines.

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Saratoga, CA, United States of America

Wanli Chang