Toshiba Memory Corporation

Wangying Lin

Shunsuke Kodera

Shinya Takeda

Yoshio Furuyama

Tetsuya Iwata

Kenichirou Kada

Kiyotaka Hayashi

A memory system includes a controller that recognizes, as a command, a signal received immediately after a chip select signal is received from a host device, and a memory that includes a plurality of blocks. When the command is a first command, the controller outputs to the host device, information indicating whether at least one of a write operation and an erase operation with respect to at least one particular block is prohibited.

Memory system storing block protection information

According to an embodiment, a semiconductor storage device includes a detection circuit configured to detect an error in data read from a first memory cell array. The read data of a size corresponding to a page unit is subjected to detection of an error for each of a plurality of first units into which the page unit is divided. When performing a first operation of concurrently executing outputting of first data read from the first memory cell array to an outside and reading of second data different from the first data from the first memory array, an interface circuit is configured to output information based on the error detected with respect to the first data to the outside.

NAND flash memory device

Growing community of inventors

Kawasaki Kanagawa, Japan

Wangying Lin