Nxp Usa, Inc.

Freescale Semiconductor,inc.

Wangsheng Mei

Yan Xiao

Liang Zhang

Martin Mienkina

Kun Wu

Joseph Charles Circello

Jianzhou Wu

Wei Luo

Gang Shi

Jun Zhang

Zhijun Chen

Zhiling Sui

Yan Huang

Yonggang Chen

Ben Wang

Michael Galda

Xiangdong Lu

Prashant U Naphade

Paulo C Knirsch

A hardware interface component arranged to operably couple at least one arithmetic unit to a an interconnect component of a processing system. The hardware interface component comprises a plurality of program-visible registers and at least one operation decoder component. The at least one operation decoder component is arranged to, upon receipt of a write access request via the interconnect component corresponding to a decorated memory-mapped address range for the hardware interface component, decode a register identifier component of a target address of the received write access request to identify at least one of the program-visible registers, decode a decoration component of the target address of the received write access request to identify an arithmetic operation to be performed, and configure the arithmetic unit to perform the identified arithmetic operation on at least one input operand within the identified at least one program-visible register.

Hardware interface component for processing write access requests that identify a register using lesser significant bits of a target address and identify an arithmetic operation to be performed using greater significant bits of the target address

A DMA controller includes a built-in timing sequence generator that allows the DMA controller to trigger data movement periodically and/or non-equidistantly, without waking a CPU or other peripherals.

DMA controller with trigger sequence generator

A touch sensor includes electrodes that are serially arranged and a processor with multiple input terminals. The electrodes are grouped into first, second and third groups of electrodes. Each electrode of the first group is coupled with a corresponding input terminal of the processor. The electrodes of the second group are sequentially coupled with the input terminals of the processor by way of odd numbered electrodes of the first group. The electrodes of the third group are sequentially coupled with the input terminals of the processor by way of even numbered electrodes of the first group. Each of the electrodes, other than the electrodes on the ends, is triggered simultaneously with at least one of its neighboring electrodes to provide sensed signals to the processor.

Touch sensor and method for determining touch position by grouping electrodes

A digital signal processor (DSP) includes a CPU, and a DMA controller. The DMA controller transfers data from a source to a destination as a function of an initialization command from the CPU. The DMA controller has a logic unit that performs filter operations and other arithmetic operations on-the-fly on a data stream transferred therethrough. The filter operations include multiplication by filter coefficients and addition, without processing by the CPU. The DMA controller may have subsets of hardware configurations that can perform different operations that are selectable as a function of the initialization command.

DMA controller with arithmetic unit

An apparatus for system design verification has a test case module for compiling a test case in a scripting language (such as TCL) and a testbench including the design under test and operating with a Hardware Descriptor Language (such as SystemVerilog). A stimulus generated by the test case module is applied to the testbench through an interface gasket based on 'C'.

Method and apparatus for system design verification

A true random number generator (RNG) has one or more oscillators and an output register for storing a random number output. Each of the oscillators is activated, successively, in a free-running oscillation phase, and a capture phase during which the oscillator is quiescent. The output register latches during the capture phase of each oscillator an end state of that oscillator at or close to the end of its oscillation phase. The random number output is derived from the latched end states.

True random number generator with repeatedly activated oscillator

A demodulator suitable for demodulating binary FSK signals having a small difference between carrier frequencies uses a counter-timer technique for timing a fixed number FSK cycles and comparing a count value with a threshold when a frequency change is expected. By grouping a number of FSK pulses (or cycles) together in one measurement, speed requirements on the system clock used for the counter/timer measurements can be relaxed and tolerance to noise is also improved. The demodulator is particularly suitable for wireless charging applications.

FSK demodulator

A sensor for sensing proximity or touch of an object includes a sensing region, an oscillating signal generator for generating an oscillating signal having an oscillation period, a gating signal generator for generating a gating signal having a gating duration, a controller for controlling the oscillation period or the gating duration and a processor for determining a number N of oscillation periods over the gating duration. The number N is indicative of the object's contact with, or proximity to, the sensing region. The sensor is calibrated by determining an optimal value for the oscillation period or gating duration such that an optimal number N over the gating duration is expected.

Proximity or touch sensor

A touch sensor interface includes one or more touch detection electrodes whose capacitance increases when touched. A processor converts the increase in capacitance into a change in a counter value. A detector compares the change in the counter value with one or more count thresholds to detect faults in the touch sensor interface.

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Suzhou, China

Wangsheng Mei