Samsung Display Co., Ltd.

Samsung Mobile Display Co., Ltd.

Wang Jo Lee

Jin Hee Jeon

Chul Ho Kim

Na Young Kim

Dong Hwi Kim

Seung Chan Lee

Beom Soo Park

Seong Jun Lee

Sang Moo Choi

Na-Young Kim

Bo Yong Chung

Jae Ik Lim

Hyung Soo Kim

Dong-Hwi Kim

Jin-Whan Jung

Jae Bum Cho

Youngmin Kwon

Yoon Ah Choi

A pixel is disclosed that includes a light emitting element connected between a first power line and a second power line; a first transistor connected between the first power line and a first electrode of the light emitting element, and having a gate electrode connected to a first node; a second transistor connected between a data line and a second node, and having a gate electrode electrically connected to a first scan line; a third transistor connected between the second node and a third node, having a gate electrode electrically connected to a first light emission control line; and a first capacitor connected between the first node and the third node.

Pixel and display device including the same

A light-emitting display device includes a first transistor including a driving gate electrode, a first electrode, and a second electrode, a storage capacitor including a first electrode and a second electrode connected to the driving gate electrode, a second transistor connected to the second electrode of the storage capacitor, a first hold capacitor including a first electrode connected to the second electrode of the storage capacitor and a second electrode to which a driving voltage is applied, a second hold capacitor including a first electrode connected to the second electrode of the storage capacitor and a second electrode to which a driving voltage is applied, a third transistor connecting the driving gate electrode and the second electrode of the first transistor, and a light-emitting diode. Conductive layers in which the first electrode of the first hold capacitor and the first electrode of the second hold capacitor are disposed are different.

Light emitting display device

A pixel circuit includes first to fifth transistors, a capacitor, and a light emitting element. The first transistor is coupled between first and second power lines, and includes a gate electrode coupled to a first node and a back-gate electrode coupled to a second node. The second transistor is coupled between a data line and the first node, and includes a gate electrode coupled to a first scan line. The third transistor is coupled between a third power line and the first node, and includes a gate electrode coupled to a reference scan line. The fourth transistor is coupled between a second node and a fourth power line, and includes a gate electrode coupled to a second scan line. The fifth transistor is coupled between a first power line and the one electrode of the first transistor, and includes a gate electrode coupled to a light-emitting control line.

Pixel circuit and display device including the same

A display device includes: a substrate; a polycrystalline semiconductor layer which includes a first electrode, a channel, and a second electrode of a driving transistor disposed on the substrate; a first gate insulating layer disposed on the polycrystalline semiconductor layer; a gate electrode of the driving transistor which is disposed on the first gate insulating layer and overlaps the channel; a lower first scan line disposed on the first gate insulating layer; a second gate insulating layer disposed on the gate electrode and on the lower first scan line; a first lower boost electrode disposed on the second gate insulating layer; a first interlayer-insulating layer disposed on the first lower boost electrode; an oxide semiconductor layer disposed on the first interlayer-insulating layer and including a first upper boost electrode overlapping the first lower boost electrode; and a first connection electrode connecting the gate electrode and the first upper boost electrode.

Display device

A pixel includes: a driving transistor including a gate electrode coupled to a first node, a first electrode coupled to a second node, and a second electrode coupled to a third node; a first initialization transistor coupled between the first node and a first initialization voltage line, and including a gate electrode coupled to a scan line, where the first initialization voltage line is configured to supply a first initialization voltage; a first emission control transistor coupled between a fourth node and a fifth node and including a gate electrode coupled to the first node; a second emission control transistor coupled between the third node and the fifth node and including a gate electrode coupled to an emission control line; and a light-emitting element coupled between the fourth node and a driving low voltage line. The driving transistor and the first emission control transistor are different types of transistors.

Pixel and display device having the same

A display device includes: a substrate including a display area at which a pixel including a light emitting element is located and a peripheral area surrounding the display area; and a common voltage line on the substrate, the common voltage line configured to provide a common voltage to the pixel, the common voltage line including: a peripheral common voltage line on the peripheral area of the substrate to surround the display area and connected to a common electrode of the light emitting element; and a plurality of display common voltage lines crossing the display area and each contacting different portions of the peripheral common voltage line, the display common voltage lines being spaced apart from the common electrode of the light emitting element.

Display device having peripheral common voltage line

A logic gate includes a first driver to receive an input signal, and to control a connection between a first power source and a first node in correspondence with the input signal, a second driver coupled to the first node and a second power source, and to control a voltage of the first node, a third driver to control a connection between an output terminal and the first power source in correspondence with the voltage of the first node, a control transistor to control a connection between the third driver and the second power source, a fourth driver to control a connection between a gate electrode of the control transistor and the second power source, and a second capacitor between a first electrode of the control transistor and the gate electrode of the control transistor, wherein the transistors are a same type of MOS transistor.

Growing community of inventors

Suwon-si, South Korea

Wang Jo Lee