Samsung Electronics Co., Ltd.

Wang-chul Shin

Jeong-Hyuk Choi

Jeong-hyuk Choi

Jin-Hyun Shin

Kyung-joong Joo

Kyong-moo Mang

Jeong-eui Kang

A method of fabricating a flash memory device. Parallel mask patterns are formed on a substrate. The substrate is etched using the mask patterns to form trenches. An insulating layer pattern is formed in the trenches and an area between the mask patterns. The mask patterns are removed to expose an upper sidewall of the insulating layer pattern that protrudes away from a top surface of the substrate. The insulating layer pattern is isotropically etched to form sloped sidewalls that protrude away from the top surface of the substrate.

Methods of fabricating flash memory devices having a sloped trench isolation structure

Flash memory devices having a sloped trench isolation structure

Methods of forming nonvolatile integrated circuit memory devices having high capacitive coupling ratios include the steps of forming a tunneling oxide layer on a face of a semiconductor substrate and then forming a forming a first conductive layer (e.g., doped polysilicon) on the tunneling oxide layer. A floating gate electrode mask is then patterned on the first conductive layer so as to expose a portion the first conductive layer. A second conductive layer is then patterned on the exposed portion of the first conductive layer and on sidewalls of the floating gate electrode mask, to define a concave or U-shaped floating gate electrode having conductive sidewall extensions. The sidewall extensions increase the effective area of the floating gate electrode and increase the capacitance coupling ratio which enables programming and erasing at reduced voltage levels. A first electrically insulating layer is then formed on the U-shaped floating gate electrode, opposite the tunneling oxide layer. A control gate is then formed on the first electrically insulating layer, opposite the U-shaped floating gate electrode.

Methods of forming nonvolatile integrated circuit memory devices having high capacitive coupling ratios

A method of manufacturing a non-volatile memory device is provided. According to an aspect of this method, an isolation layer is formed on a semiconductor substrate including a cell array part and a peripheral circuit part. A floating gate pattern is formed exposing the semiconductor substrate in the peripheral circuit part with a tunnel oxide layer interposed between the floating gate pattern and the semiconductor substrate in the cell array part, and an interlayer insulating layer covering the floating gate pattern is formed. A control gate layer is formed, which covers the interlayer insulating layer and the semiconductor substrate in the peripheral circuit part while interposing a gate oxide layer between the control gate layer and the semiconductor substrate. The isolation layer in the peripheral circuit part is protected by leaving a part of the control gate layer covering the peripheral circuit part, and a control gate, an interlayer insulating layer pattern, and a floating gate in the cell array part are formed by sequentially patterning the control gate layer, the interlayer insulating layer, and the floating gate pattern in the cell array part. A first low-concentration impurity layer is formed by first ion-implantation of arsenic into the semiconductor substrate adjacent to the floating gate using the control gate and the control gate layer covering the peripheral circuit part as an ion-implantation mask. A gate is formed in the peripheral circuit part by patterning the control gate layer in the peripheral circuit part with a photo resist pattern shielding the cell array part. A second low-concentration impurity layer is formed by second ion-implantation of second impurities, phosphorous, into the semiconductor substrate adjacent to the gate using the photo resist pattern as an ion-implantation mask.

Method of manufacturing non-volatile memory device

A flash memory device for providing high integration and high-speed data access has string blocks arranged in a two-dimensional manner. Each string block has a plurality of strings, at least one bit line select line, a plurality of word lines, a plurality of source line select lines, a first dual-mode line, and a second dual-mode line. Each string is constructed such that at least one bit line select transistor, a plurality of unit memory cells, and a plurality of source line select transistors are connected in series. The bit line select lines are connected to respective gates of the bit line select transistors. The plurality of word lines are connected to respective control gates of the plurality of unit memory cells. The first dual-mode line is connected to one end of each of the strings in a first string block through a bit line contact, and the second dual-mode line is connected to other end of each of the strings in the first string block through a source line contact. Additionally, the first dual-mode line is connected to the source line contact of a second string block while the second dual-mode line is connected to the bit line contact of a third string block.

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Gyeonggi-do, South Korea

Wang-chul Shin