Faraday Technology Corporation

Wang-Chin Chen

Shyh-An Chi

Augusli Kifli

Po-Chen Lo

Chun-Sung Su

Shang-Ru Lin

Yi-Yeh Yang

Jen-Hsing Lin

Jin-Cheng Chen

A power distribution network adapted to provide power to a plurality of components in an integrated circuit is provided. The power distribution network includes a power distribution trunk path, a plurality of first power distribution branch paths, and a plurality of second power distribution branch paths. The power distribution trunk path is used for transmitting the power. A long axis direction of the power distribution trunk path is a first direction. The first power distribution branch paths and the second power distribution branch paths are electrically connected to the power distribution trunk path. A long axis direction of the first power distribution branch paths is a second direction different from the first direction. A long axis direction of the second power distribution branch paths is a third direction different from the first direction and the second direction.

Power distribution network of integrated circuit

The invention provides an internal comparison circuits for speeding up the ATPG test. During test, an external test machine transfers original test patterns into at least one scan chain of a chip to be tested. A bi-directional output buffer of the chip also receives the test patterns from the test machine. A comparator of the chip compares the original test patterns from the test machine via the bi-directional output buffer group with scanned-out test patterns from the scan chain, to produce a comparison signal indicating whether the chip passes or fails the test.

High speed ATPG testing circuit and method

A switch controlling circuit, which comprises: a frequency programmable clock signal generator and a plurality of registers. The frequency programmable clock signal generator serves to generate a frequency controllable clock signal. The registers comprises: a first stage register, for receiving an input signal and the frequency controllable clock signal, and for outputting a first output signal, which is utilized to control a first switch device, according to the input signal and the frequency controllable clock signal; and a second stage register, for receiving the first output signal and the frequency controllable clock signal, and for outputting a second output signal, which is utilized to control a second switch device, according to the first output signal and the frequency controllable clock signal.

Switch controlling circuit, switch circuit utilizing the switch controlling circuit and methods thereof

For on-chip testing an on-chip power switch coupled to a core logic and to a decoupling capacitance, after the power switch enters a test mode, the decoupling capacitance is pre-charged or discharged; the power switch is turned ON or OFF according to test patterns; and a voltage level at the decoupling capacitance is analyzed or a leakage current flowing the power switch is measured. So that, whether the power switch is passed or failed is identified.

Test circuit and test method for power switch

A parametric measuring circuit for minimizing an oscillation effect is provided. The parametric measuring circuit comprises an input detection circuit, an oscillation effect eliminating logic circuit and an output selection circuit. The input detection circuit receives an input signal from an external input terminal and outputs the detection signal. The oscillation effect eliminating logic circuit is coupled to the input detection circuit for reducing/eliminating oscillation effect and outputting the detection signal. The output selection circuit is coupled to the oscillation effect eliminating logic circuit to select and transmit either the output signal generated from the internal circuit or the detection signal to the output terminal.

Growing community of inventors

Kaohsiung County, Taiwan

Wang-Chin Chen