Sandisk Technologies Inc.

Wanfang Tsai

YenLung Li

Chen Chen

Eran Sharon

Yan Li

Idan Alrod

Ariel Navon

Chang Hua Siau

Gopinath Balakrishnan

Yosuke Kato

Alexander Tsang-Nam Chu

Shingo Zaitsu

Hung-Szu Lin

Yi-Fang Chen

Apparatuses and techniques for counting 0 or 1 bits in a set of bits using both serial and parallel processes. The counting process includes a hierarchy in which the count from different parallel processes at one level in the hierarchy are passed to a smaller number of different parallel processes at a lower level in the hierarchy. A final count is obtained by an accumulator below the lowest level of the hierarchy. The position and configuration of the circuits can be set to equalize a number of circuits which process the different bits, so that a maximum delay relative to the accumulator is equalized.

Hierarchical fail bit counting circuit in memory device

Systems and methods for controlling data flow and data alignment using data expand and compress circuitry arranged between a variable data rate bi-directional first in, first out (FIFO) buffer and one or more memory arrays to compensate for bad column locations within the one or more memory arrays are described. The bi-directional FIFO may have a variable data rate with the array side and a fixed data rate with a serializer/deserializer (SERDES) circuit that drives input/output (I/O) circuitry. The data expand and compress circuitry may pack and unpack data and then align the data passing between the one or more memory arrays and the bi-directional FIFO using a temporary buffer, data shuffling logic, and selective pipeline stalls.

Bad column management with data shuffle in pipeline

A data storage device includes a set of latches, read/write circuitry, a memory, and an interleaver. The set of latches is configured to receive data. The read/write circuitry is coupled to the set of latches. The memory is coupled to the read/write circuitry. The interleaver is configured to interleave the data and to cause the read/write circuitry to program the interleaved data to the memory. The set of latches, the read/write circuitry, the memory, and the interleaver are integrated within a common die.

Data storage device with a memory die that includes an interleaver

Sensing techniques and associated circuitry are provided for use with a memory device. The techniques are suited for sensing operations involving even-numbered or odd-numbered bit lines. In one approach, the sensing circuitry includes left and right hand portions which have separate cache access lines, but are connected to a common output bus. A full data word can be output at a time by using a half word from the left hand portion and a half word from the right hand portion. Or, the sensing circuitry can be configured so that a full data word is output at a time from the left or right hand portion. One implementation provides an N-bit bus and N input paths for each of the left and right hand portions. Another implementation provides an N-bit bus and N/2 input paths for each of the left and right hand portions.

Fast read for non-volatile storage

A memory circuit includes an array subdivided into multiple divisions, each connectable to a corresponding set of access circuitry. A serializer/deserializer circuit is connected to a data bus and the access circuitry to convert data between a (word-wise) serial format on the bus and (multi-word) parallel format for the access circuitry. Column redundancy circuitry is connect to the serializer/deserializer circuit to provide defective column information about the array. In converting data from a serial to a parallel format, the serializer/deserializer circuit skips words of the data in the parallel format based on the defective column information indicating that the location corresponds to a defective column. In converting data from a parallel to a serial format the serializer/deserializer circuit skips words of the data in the parallel format based on the defective column information indicating that the location corresponds to a defective column.

Centralized variable rate serializer and deserializer for bad column management

A shift register structure is presented that can be used in variable rate parallel to serial data conversions. In an N to 1 conversion, data is received from an (N&#xd7;m)-wide parallel data bus in an N by m wide latch. This data can include m-bit wide units of data are to be ignore and the parallel bus clock will be of variable rate due to this data to be skipped, which is not to be put out on to the serial bus. The data is transferred from the latch to an N unit shift register, each unit holding m-bits. Multiplexing circuitry is included so that at least on unit of the shift can receive data from more than one latch location, thereby reducing the number of units in the shift register that may need to be skipped when the data is transferred out on to an m-bit wide serial bus with the bits to be ignored absent.

Variable rate parallel to serial shift register

A shift register structure is presented that can be used in fixed or variable rate serial to parallel data conversions. In an 1 to N conversion, data is received off an m-bit serial data bus and loaded into a N by m wide latch, before being transfer out onto an (N&#xd7;m)-wide parallel data bus. Based on information on how of the N m-bit wide data units are to be ignored, the data will be clocked out at a variable rate. When loading data off the serial bus into the latch, upon refresh the current data is loaded into all N units of the latch, with one less latch being loaded at each subsequent clock. When the content of a unit of latch is to be ignored on the parallel bus, that unit is closed at the same time as the preceding unit so that it is left with redundant data.

Variable rate serial to parallel shift register

Techniques are present for locating an initial physical location in a looping shift register with random skips on each loop. Here the shift register is for accessing columns in a non-volatile memory, where defective columns of the array are skipped. A look-up table provides for the initial skip of each loop, providing the number of skips from preceding loop to provide a physical address is close to the actual physical address. A new structure of shift registers then enables an automatic shift mode within the loop. The new structure has an additional register and logic gates that count how many skipped entry before the current pointer and shift the current pointer accordingly.

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Mountain View, CA, United States of America

Wanfang Tsai