Taiwan Semiconductor Manufacturing Comp. Ltd.

Au Optronics Corporation

Wan-Yu Lo

Kuo-Nan Yang

Chin-Shen Lin

Chung-Hsing Wang

Meng-Xiang Lee

Chung-Min Fu

Hiranmay Biswas

Hao-Tien Kan

Chin-Chou Liu

Ming-Hsien Lin

Yu-Cheng Chen

Tsan-Chun Wang

Huan Chi Tseng

Chung-hsing Wang

Po-Hsueh Chen

Wei-Jen Chang

Jhih-Hong Ye

Chih-Liang Chen

Yung-Chow Peng

Po-Hsiang Huang

Dian-Hau Chen

Sheng-Hsiung Chen

Wen-Hao Chen

Cheng-Chieh Hsieh

Yuan-Te Hou

Chi-Yu Lu

Hsiang-Ku Shen

Huang-Yu Chen

Shao-Huan Wang

Maw-Song Chen

Chung-Kai Lin

Meng-Fu You

Yu-Jen Chang

Chih-Yeh Yu

Shih-Cheng Yang

A method of forming a semiconductor arrangement includes forming a first capacitor in a first voltage domain and forming a second capacitor in the first voltage domain. The first capacitor is connected in parallel with the second capacitor. A third capacitor and a fourth capacitor are formed in a second voltage domain. The third capacitor is connected in series with the fourth capacitor. The first capacitor and the second capacitor are connected in parallel with a supply terminal of the first voltage domain and a reference terminal of the first voltage domain. The fourth capacitor is connected to a supply terminal of the second voltage domain. The third capacitor is connected to a reference terminal of the second voltage domain.

Semiconductor arrangement and method of making

Semiconductor devices are provided. A semiconductor device includes a semiconductor substrate, a power switch, a first power mesh and a second power mesh. The power switch is formed over the front surface of the semiconductor substrate. The first power mesh is formed over the power switch and is directly connected to the first terminal of the power switch. The second power mesh is formed over the back surface of the semiconductor substrate and is directly connected to the second terminal of the power switch.

Semiconductor device including frontside power mesh and backside power mesh and manufacturing method thereof

Various layouts for conductive interconnects in the conductor layers in an integrated circuit are disclosed. Some or all of the conductive interconnects are included in a power delivery system. In general, the conductive interconnects in a first conductor layer are arranged according to an orthogonal layout and the conductive interconnects in a second conductor layer are arranged according to a non-orthogonal layout. Conductive stripes in a transition conductor layer positioned between the first and the second conductor layers electrically connect the conductive interconnects in the first conductor layer to the conductive interconnects in the second conductor layer.

Layouts for conductive layers in integrated circuits

In a method, cell placement is performed to place a plurality of cells into a region of an integrated circuit (IC). A thermal analysis is performed to determine whether the region of the IC is thermally stable at an operating condition. In response to a determination that the region of the IC is thermally unstable, at least one of a structure or the operating condition of the region of the IC is changed. After the thermal analysis, routing is performed to route a plurality of nets interconnecting the placed cells. At least one of the cell placement, the thermal analysis, the changing or the routing is executed by a processor.

Integrated circuit design method, system and computer program product

A method of forming a semiconductor device including: providing a first circuit cell including a first pin cell; forming a connecting path originated from the first pin cell of the first circuit cell; performing an Electromigration (EM) checking process with a first parasitic capacitance of the first pin cell and a second parasitic capacitance of the connecting path by loading a loading capacitance file to determine whether the loading capacitance of the first pin cell is larger than a first predetermined capacitance; and substituting a second pin cell for the first pin cell when the loading capacitance of the first pin cell is larger than the first predetermined capacitance, wherein the second pin cell is different from the first pin cell.

Method and system of forming semiconductor device

The present disclosure provides a routing structure. The routing structure includes a substrate having a boundary and a first conductive trace configured to be coupled to a first conductive pad disposed within the boundary of the substrate. The first conductive trace is inclined with respect to the boundary of the substrate.

Routing structure

A method for manufacturing a semiconductor device is provided. The method comprises determining a dimensional quantity of a layout pattern having an angle relative to grid lines of a minimum grid. The minimum grid may be defined by a first quantity associated with a first direction and a second quantity associated with a second direction perpendicular to the first direction. The determination of the dimensional quantity of the layout pattern is based on the first quantity, the second quantity and the angle of the layout pattern relative to the grid lines of the minimum grid.

Circuit layouts and related methods

Methods for analyzing electromigration (EM) in an integrated circuit (IC) are provided. A layout of the IC is obtained. A metal segment is selected from the layout according to a current simulation result of the IC. Two first vias are formed over and in contact with the metal segment in the layout. EM rule is kept on the metal segment when a distance between the two first vias is greater than a threshold distance. The EM rule is relaxed on the metal segment when the distance between the two first vias is less than or equal to the threshold distance.

Method for analyzing electromigration (EM) in integrated circuit

A method of forming a semiconductor device includes: providing a first circuit having a plurality of circuit cells; analyzing a loading capacitance on a first pin cell connecting a first circuit cell and a second circuit cell in the plurality of circuit cells to determine if the loading capacitance of the first pin cell is larger than a first predetermined capacitance; replacing the first pin cell by a second pin cell for generating a second circuit when the loading capacitance is larger than the first predetermined capacitance, wherein the second pin cell is different from the first pin cell; and generating the semiconductor device according to the second circuit.

The present disclosure provides a routing structure. The routing structure includes a substrate having a first circuit region and a boundary surrounding the first circuit region. The routing structure also includes a first conductive trace coupled to a first conductive pad disposed in the first circuit region. The first conductive trace is inclined with respect to the boundary of the substrate. A method of forming a routing structure is also disclosed.

Routing structure and method of forming the same

Methods for analyzing electromigration (EM) in an integrated circuit (IC) are provided. The layout of the IC is obtained. A metal segment is selected from the layout according to a current simulation result of the IC. EM rule is kept on the metal segment when a single via is formed over and in contact with the metal segment in the layout. The EM rule is relaxed on the metal segment when two first vias are formed over and in contact with the metal segment in the layout. The two first vias have the same current direction.

A method of forming a semiconductor device includes: providing a first circuit having a plurality of circuit cells; analyzing a loading capacitance on a first pin cell connecting a first circuit cell and a second circuit cell in the plurality of circuit cells to determine if the loading capacitance of the first pin cell is larger than a first predetermined capacitance; replacing the first pin cell by a second pin cell for generating a second circuit when the loading capacitance is larger than the first predetermined capacitances, wherein the second pin cell is different from the first pin cell; and generating the semiconductor device according to the second circuit.

In a method, based on an operating condition of a region of an integrated circuit (IC), a first relationship between a temperature and heating power of the region is determined. Based on a cooling capacity of the region, a second relationship between the temperature and cooling power of the region is determined. Based on the first relationship and the second relationship, it is determined whether the region is thermally stable. In response to a determination that the region is thermally unstable, at least one of a structure or the operating condition of the region is changed. At least one of the determination of the first relationship, the determination of the second relationship, the determination of thermally stability of the region, or the change of at least one of the structure or the operating condition of the region is executed by a processor.

Methods for analyzing electromigration (EM) in an integrated circuit (IC) are provided. The layout of the IC is obtained. A metal segment is selected from the layout according to the current simulation result of the IC. It is determined whether to relax the EM rule on the metal segment according to the number of vias over the metal segment in the layout. The vias are in contact with the metal segment.

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Taoyuan County, Taiwan

Wan-Yu Lo