Taiwan Semiconductor Manufacturing Comp. Ltd.

Haynes and Boone, Llp

Wan-Yu Lee

Ying-Hao Kuo

Chun-Hao Tseng

Tien-I Bao

Hai-Ching Chen

Kuo-Chung Yee

Jui Hsieh Lai

Tien-Yu Huang

Shang-Yun Hou

Yu-Hsiang Hu

Li-Hsien Huang

Hua-Wei Tseng

Yueh-Ting Lin

Chiang Lin

Sung-Hui Huang

Sao-Ling Chiu

Hung-Pin Chang

Chia-Hao Hsu

Kuo-Chiang Ting

Tu-Hao Yu

Weiming Chris Chen

Ting-Yu Yeh

Yu-Jie Su

Tien-l Bao

A method includes forming a reconstructed wafer including encapsulating a device die in an encapsulant, forming a dielectric layer over the device die and the encapsulant, forming a plurality of redistribution lines extending into the dielectric layer to electrically couple to the device die, and forming a metal ring in a common process for forming the plurality of redistribution lines. The metal ring encircles the plurality of redistribution lines, and the metal ring extends into scribe lines of the reconstructed wafer. A die-saw process is performed along scribe lines of the reconstructed wafer to separate a package from the reconstructed wafer. The package includes the device die and at least a portion of the metal ring.

Air channel formation in packaging process

A method of forming an optical bench includes forming a reflector layer over a sloping side of a substrate. The method includes depositing a redistribution layer over the substrate. The method includes disposing an under bump metallization (UBM) layer over the redistribution layer. The method includes forming a passivation layer over the redistribution layer and surrounding sidewalls of the UBM layer. The method includes mounting a first optical component over an uppermost portion of the substrate, wherein the reflector layer is configured to reflect an electromagnetic wave from the first optical component, and the first optical component is mounted outside the trench.

Optical bench, method of making and method of using

A method includes filling a trench formed in a first integrated circuit carrier with temporary bonding material to form a temporary bonding layer. At least one chip is bonded over the temporary bonding layer.

Temporary bonding scheme

A semiconductor package structure includes a first package, a second package over the first package, a plurality of connectors between the first package and the second package and a plurality of baffle structures between the first package and the second package. The second package includes a bonding region and a periphery region surrounding the bonding region. The connectors are disposed in the bonding region to provide electrical connections between the first package and the second package. The baffle structures are disposed in the periphery region and are separated from each other.

Semiconductor package structure and method for manufacturing the same

A method of fabricating a waveguide device is disclosed. The method includes providing a substrate having an elector-interconnection region and a waveguide region and forming a patterned dielectric layer and a patterned redistribution layer (RDL) over the substrate in the electro-interconnection region. The method also includes bonding the patterned RDL to a vertical-cavity surface-emitting laser (VCSEL) through a bonding stack. A reflecting-mirror trench is formed in the substrate in the waveguide region, and a reflecting layer is formed over a reflecting-mirror region inside the waveguide region. The method further includes forming and patterning a bottom cladding layer in a wave-tunnel region inside the waveguide region and forming and patterning a core layer and a top cladding layer in the waveguide region.

Method of fabrication polymer waveguide

An embodiment method includes bonding a first die to a first side of an interposer, the interposer comprising a substrate; after bonding the first die to the first side of the interposer, depositing a first insulating layer on a second side of the interposer opposite the first side; patterning an opening through the substrate and the first insulating layer; and depositing a second insulating layer over the first insulating layer and along sidewalls and a lateral surface of the opening. The second insulating layer comprises silicon. The method further includes removing lateral portions of the second insulating layer to define a sidewall spacer on sidewalls of the opening and forming a through via in the opening, wherein the through via is electrically connected to the first die.

Conductive vias in semiconductor packages and methods of forming same

A system and method for manufacturing semiconductor devices is provided. An embodiment comprises using an etchant to remove a portion of a substrate to form an opening with a 45&#xb0; angle with a major surface of the substrate. The etchant comprises a base, a surfactant, and an oxidant. The oxidant may be hydrogen peroxide.

Etchant and etching process for substrate of a semiconductor device

An optical bench including a substrate having a trench with the trench having an angled sidewall on which a reflective coating is provided. The optical bench also includes a first device and a waveguide positioned within the trench, a second device optically connected to the first device, and at least one active circuit electrically connected to the first device with the waveguide being positioned optically between the first device and the reflective coating. The optical bench also includes an optically transparent material that forms a first interface with the first device and a second interface with a first surface of the waveguide.

Optical bench on substrate and method of making the same

An electro-optic modulator device includes a modulation region, a reflecting region, a conductive line and an anti-reflecting region. The modulation region includes a doped region. The reflecting region is over the modulation region. The conductive line is connected to the doped region. The conductive line extends through the reflecting region. The anti-reflecting region is on an opposite surface of the modulation region from the reflecting region.

Electro-optic modulator device, optical device and method of making an optical device

In some embodiments, the present disclosure relates to a package for holding a plurality of integrated circuits. The package includes a first conductive pad disposed over a first substrate and a second conductive pad disposed over a second substrate. The second conductive pad is a multi-layer structure having an uppermost metal layer including titanium or nickel. A molding structure surrounds the first substrate and the second substrate. A conductive structure is over the first substrate and the second substrate. The conductive structure is conductively coupled to the second conductive pad.

Package and method for integration of heterogeneous integrated circuits

A method of making an optical bench includes forming a trench in a substrate and wherein the trench has a sloping side, forming a reflector layer over the sloping side, depositing a redistribution layer over the substrate, disposing an under bump metallization (UBM) layer over the redistribution layer, depositing a passivation layer over the redistribution layer and surrounding sidewalls of the UBM layer, and mounting an optical component over an uppermost portion of the substrate, wherein the optical component is electrically connected to a through substrate via (TSV) extending through the substrate. The reflector layer is configured to reflect an electromagnetic wave from the optical component, and wherein the optical component is mounted outside the trench.

Optical bench on substrate

A backside-illuminated photodetector structure includes a first reflecting region, a second reflecting region and a semiconductor region. The semiconductor region is between the first reflecting region and the second reflecting region. The semiconductor region comprises a first doped region and a second doped region.

Growing community of inventors

Taipei, Taiwan

Wan-Yu Lee