Vanguard International Semiconductor Corporation

Worldwide Semiconductor Manufacturing Corporation

Worldwide Semiconductor Mfg. Corp.

Wan-Yih Lien

Hao-Chieh Liu

Fu-Liang Yang

Wen-Shiang Liao

Erik S Jeng

Kung Linliu

Tzu-Shih Yen

Bi-Ling Chen

Sen-Huan Huang

Yeur-Luen Tu

Meng-Jaw Cherng

Meng-Jaw Cheng

Yi-Ping Lee

A structure of dynamic random access memory with slanted active regions, comprising: a substrate; a plurality of slanted active regions formed on the substrate, wherein each of the plurality of slanted active regions has a bit line contact; a plurality of word line regions formed on the substrate to control transistors of the dynamic random access memory; a plurality of bit line regions formed on the substrate, wherein each of the bit line regions cross the bit line contact hole so that the bit line contact hole is completely covered by the bit line regions; a plurality of capacitors formed between the plurality of bit line regions.

Dynamic random access memory with slanted active regions

The invention describes a self-aligned etching process. A conductive layer and a first insulating layer are formed on a substrate in sequence, and then the conductive layer and the first insulating layer are patterned to form a plurality of stacks on desired regions. Subsequently, spacers are formed on sidewalls of each stack, and a stop layer is then formed on the substrate. A second insulating layer is formed on the substrate and is planarized. Portions of the second insulating layer are removed to form a plurality of openings and to expose portions of the stop layer located between spacers. The exposed stop layer is removed.

Self-aligned eetching process

A method for manufacturing dynamic random access memory (DRAM) capacitor. A first insulation layer having a plurality of first plugs and second plugs therein is formed over a substrate. A plurality of bit lines is formed over the first insulation layer. Each bit line has a multiple of bit line contacts, and each bit line contact is connected electrically to one of the first plugs. A cap layer is formed on top of the bit lines and spacers are formed on the sidewalls of the bit lines. The spacers are formed in such a way that they are linked near the bit line contact of every pair of neighboring bit lines. A planarized second insulation layer is formed over the substrate. Using the cap layers, the spacers and the second plugs as stopping points, an etching operation is carried out to form the lower electrode openings of capacitors and node contact openings. A conformal conductive layer that covers the exposed surfaces of the electrode openings and the node contact openings are formed, hence forming the lower electrode of a capacitor. A dielectric layer is formed over the lower electrode, and finally an upper electrode is formed over the dielectric layer to form a complete capacitor.

Method for manufacturing DRAM capacitor

A process for forming a tungsten plug structure, in a contact hole, without recessing of the tungsten plug, or of the adhesive and barrier layers, located on the sides of the contact hole, during the tungsten plug patterning procedure, has been developed. The process features a two stage, in situ RIE procedure, in which a photoresist shape, larger in width than the diameter of the contact hole, is used as a mask to allow patterning of an aluminum based layer, of an underlying tungsten, and of the barrier and adhesive layers. The result of the two stage, in situ RIE procedure is an aluminum based interconnect structure, overlying a tungsten plug structure, with the tungsten plug structure comprised of a tungsten plug, in a contact hole, protected during the patterning procedure by the overlying aluminum based interconnect structure.

Method for fabricating a tungsten plug structure and an overlying

A method for controlling the thickness of a passivation layer underlying with a fuse on a semiconductor device is disclosed herein. The anti-reflective coating on a metal layer is buried in the passivation layer, and the fuse is in a semiconductor device. The method includes the following steps. First, use a first etchant and Ar to etch the passivation layer till the anti-reflective coating is exposed, the first thickness of the passivation layer above the anti-reflective coating is smaller than the second thickness of the passivation layer above the fuse. Then, utilize a second etchant to etch the anti-reflective coating till the metal layer is exposed. The second etchant has a selectivity ratio from the anti-reflective coating to the passivation layer being at least 10. The second etchant mentioned above includes BCl.sub.3, Cl.sub.2, O.sub.2, and Ar.

Method for controlling the thickness of a passivation layer on a

A method for creating a metal filled, high aspect ratio, contact opening, in thick insulator layers, allowing contact between a metal interconnect structure and a region of a semiconductor substrate, has been developed. The process features creating a stacked contact hole opening, comprised of a upper contact hole opening, of a specific diameter size, overlying a lower contact hole opening, having an opening larger in diameter than the opening used for the upper contact hole opening. The lower contact hole opening is created via an anisotropic RIE procedure, followed by a wet etch procedure, used to enlarge the diameter of the lower contact hole opening. The upper contact hole opening, created using an anisotropic RIE procedure, is formed using the original diameter opening, used previously for the pre-wet etched, lower contact hole opening, and is easily aligned to a metal filled, enlarged lower contact hole opening.

Method for fabricating a high aspect ratio stacked contact hole

A method of forming a plurality of contact holes 70 in a semiconductor wafer uses a single step. The semiconductor wafer includes a dielectric layer 69 overlying a silicon substrate 51, a silicon nitride layer 67a, and a silicon oxynitride layer 63c. First, a photoresist 68 layer is developed on the dielectric layer. Prior to forming the dielectric layer, the silicon oxynitride layer is formed overlying a first conductive layer, and the silicon nitride layer is formed overlying a second conductive layer. Second, an etching step is performed to etch through the silicon oxynitride layer, the silicon nitride layer, a portion of the dielectric layer above the silicon oxynitride layer, and the silicon nitride layer to expose the silicon substrate 51, the first conductive layer 63a, and the second conductive layer 67c. The etching recipe includes a first chemistry and a second chemistry. The first chemistry includes C.sub.2 F.sub.6, C.sub.4 F.sub.8, CH.sub.3 F, and Ar. The second chemistry is chosen from a group including O.sub.2, CO.sub.2, CO and any combination thereof. Thus, a plurality of contact holes is formed above the silicon substrate, the first conductive layer and the second conductive layer.

Method for forming multi-level contacts

A process for simultaneously forming storage node structures, for a DRAM cell, and an interconnect structure, for a peripheral region of a DRAM chip, has been developed. The process features the use of dual damascene procedures, with the first damascene procedure used to create the storage node, and interconnect structures, followed by a second damascene procedure, used to create plug structures, used to contact the underlying storage node and interconnect structures. This invention also features the use of SAC openings, allowing the formation of the SAC storage node structures to be realized.

Method for simultaneously fabricating capacitor structures, for giga-bit

A method for making low-resistance contacts between polycide layers for local interconnections is achieved. The method is particularly useful for making low contact resistance R.sub.c between the tungsten polycide layers for local interconnections on the periphery of the DRAM chip. A first polycide layer is patterned to form FET gate electrodes and portions of local interconnections. An interlevel dielectric layer is deposited over the patterned first polycide layer. Contact openings are etched in the dielectric layer to the surface of the substrate and to the first polycide layer. A second polycide layer is deposited and patterned to form bit lines in the memory cell areas of the DRAM, while concurrently forming local interconnections in the peripheral device areas. A high-temperature rapid thermal anneal (RTA) is carried out to substantially reduce the contact resistance in the contact openings over the first polycide layer in the peripheral areas. This RTA eliminates the need for overetching the first silicide in the contact holes, as commonly practiced in the prior art. The RTA of this invention with a traditional N.sub.2 anneal prior to the second polycide deposition results in a synergistic effect that further reduces the contact resistance R.sub.c.

Growing community of inventors

Hsinchu, Taiwan

Wan-Yih Lien