Macronix International Co., Ltd.

Wan-Yi Liu

Ping-Yi Chang

Pei-Ren Jeng

Chi-Tung Huang

Shu-Li Wu

The present invention provides a method for forming a flash memory cell and comprises following steps. First, a substrate is provided. Then, a gate dielectric layer, a first polysilicon layer and a hard mask layer are sequentially formed on the substrate. Next, a portion of the hard mask layer, the polysilicon layer, and the gate dielectric layer are removed to form a plurality of holes to expose the substrate. Following, a dielectric layer is formed in those holes by a HDPCVD process. Last, the hard mask layer on the first polysilicon layer is removed by the HDPCVD process. Further, a second polysilicon layer could be conformally formed on the first polysilicon layer and the isolation dielectric.

Method for forming flash memory cell

A method of forming a shallow trench isolation structure. A pad oxide layer and a mask layer are sequentially formed over a substrate. A portion of the pad oxide layer, mask layer and substrate are removed to form a trench in the substrate. A first stage high-density plasma chemical vapor deposition having a high etching/deposition ratio is conducted to form a layer of insulation material over the substrate. A second stage high-density plasma chemical vapor deposition having a lower etching/deposition rate is conducted to form a second layer of insulation material over the substrate and completely fills the trench. Insulating material outside the trench region is removed. Finally, the mask layer and the pad oxide layer are sequentially removed to form a complete STI structure.

Method of forming shallow trench isolation

The present invention provides a passivation film on a semiconductor wafer. The semiconductor wafer comprises a dielectric layer and a patterned conductive layer on the dielectric layer. The passivation film comprises a high density plasma (HDP) oxide layer positioned on the surface of the conductive layer and on the surface of the dielectric layer that is not covered by the conductive layer, a silicon nitride layer positioned on the HDP oxide layer, and a water-resistant layer positioned on the silicon nitride layer. The HDP oxide layer possesses good gap filling abilities to fill the spaces inside the conductive layer.

Passivation film on a semiconductor wafer

A method of forming memory cell having buried diffusion oxide is disclosed. The method comprises the steps of providing a substrate having a tunnel oxide layer and a first conductive layer thereon, forming trenches into said tunnel oxide layer and said first conductive layer to expose said substrate, filling said trenches with a dielectric material to a predetermined thickness, removing a portion of said first conductive layer to form a surface lower than said predetermined thickness; and forming a second conductive layer over said dielectric material and said first conductive layer.

Method of flash cell formation

A method for forming shallow trench isolation is disclosed. A pad oxide layer is formed on a substrate, and a mask layer is deposited on the pad oxide layer. The mask layer and the pad oxide layer are patterned to expose the substrate. Thereafter, the exposed substrate is subsequently etched to form a shallow trench. A lining oxide layer is formed by thermal oxidation on the shallow trench sidewalls. Afterwards, a silicon-rich oxide layer is deposited by high-density chemical vapor deposition (HDPCVD) process on the substrate and the shallow trench. Next, a silicon oxide layer is formed using the same HDPCVD process on the silicon-rich layer. Subsequently, an excess portion of silicon oxide and the silicon-rich oxide over the silicon nitride layer are effectively removed using some standard semiconductor processes. Eventually, the mask layer is removed and the pad oxide layer is stripped to form silicon oxide plug served as shallow trench isolation.

Growing community of inventors

Kaohsiung, Taiwan

Wan-Yi Liu