Taiwan Semiconductor Manufacturing Comp. Ltd.

Wan-Yen Lin

Bo-Ting Chen

Chia-Hui Chen

Yu-Ti Su

Wun-Jie Lin

Kuo-Ji Chen

Jen-Chou Tseng

Min-Chang Liang

Tsung-Hsin Yu

Sun-Jay Chang

Chia-Jung Chang

Yuan-Ju Chan

Jam-Wem Lee

Yue-Der Chih

Ming-Hsiang Song

Cheng-Hsiung Kuo

Shu-Yu Chen

Systems and methods are provided for a level shifter. A level shifter includes a network of transistors configured to receive a signal at a first node in a first voltage domain and to generate a corresponding signal at a second node in a second voltage domain during a transition period of time. A self timing circuit is configured to receive an initiation signal based on the signal at the first node and to generate a voltage transition accelerator signal that is used to pull up the second node prior to the expiration of the transition period of time.

Self timed level shifter circuit

A circuit device includes core circuitry. The circuit device further includes a first plurality of guard rings having a first dopant type, wherein the first plurality of guard rings is around a periphery of the core circuitry. The circuit device further includes a second plurality of guard rings having a second dopant type, wherein the second dopant type is opposite to the first dopant type, and at least one guard ring of the second plurality of guard rings is around a periphery of at least one guard ring of the first plurality of guard rings.

Guard ring and circuit device

A method of protecting a device (protected device) (in a semiconductor system from an electrostatic discharge (ESD)) includes: coupling the protected device between a first node and a first reference voltage; coupling an ESD device between the first node and the first reference voltage; and selectively and actively coupling an input of the ESD device to a second reference voltage thereby selectively and actively turning on the ESD device.

ESD protection circuit, semiconductor system including same, and method for operating same

A level shifter includes an input circuit having first and second input terminals configured to receive complementary input signals at a first voltage level and a second voltage level. A cross-latch circuit is coupled to the input circuit, and has first and second output terminals configured to provide complementary output signals at a third voltage level and a fourth voltage level. The input circuit includes first and second control nodes configured to output first and second control signals at the first voltage level and the fourth voltage level based on the input signals. A tracking circuit is coupled to the input circuit and the cross-latch circuit, and is configured to input first and second tracking signals to the cross-latch circuit based on the first and second control signals, wherein the first tracking signal is the greater of the first control signal and the third voltage level, and the second tracking signal is the greater of the second control signal and the third voltage level.

Level shifter

A buffer circuit includes an input terminal configured to receive an input signal, an output terminal, an inverter, and a resistor-capacitor (RC) circuit coupled in series with the inverter between the input terminal and the output terminal. The RC circuit includes an NMOS transistor coupled between an RC circuit output terminal and a reference node, a resistor coupled between the RC circuit output terminal and a power supply node, and a capacitor coupled between the RC circuit output terminal and one of the power supply node or the reference node, and the inverter and the RC circuit are configured to generate an output signal at the output terminal based on the input signal.

Logic buffer circuit and method

A method of protecting a device (protected device) in a semiconductor system from an electrostatic discharge (ESD), the protected device being coupled between a first node and a first reference voltage, the method including: coupling an ESD device between the first node and the first reference voltage; coupling a shunting device between an input of the protected device and the first reference voltage; coupling a feedback control circuit between the first node and an input of the shunting device; and using the shunting device to actively couple the input of the protected device to the first reference voltage.

A buffer circuit includes an input terminal configured to receive an input signal, an output terminal, a buffer, and an RC circuit coupled in series with the buffer between the input terminal and the output terminal. The RC circuit includes a first transistor and an RC network including a resistor and a capacitor, the first transistor is coupled in series with the resistor between a power supply node and a reference node, and the buffer and the RC circuit are configured to generate an output signal based on the input signal.

A method includes implanting a first guard ring around a periphery of core circuitry. The implanting of the first guard ring includes implanting a first component a first distance from the core circuitry on a first side of the core circuitry, and implanting a second component a second distance from the core circuitry on a second side of the core circuitry, wherein the second distance is greater than the first distance. The method further includes implanting a second guard ring around the periphery of the core circuitry. The implanting of the second guard ring includes implanting a third component a third distance from the core circuitry on the first side of the core circuitry, and implanting a fourth component a fourth distance from the core circuitry on the second side of the core circuitry, wherein the third distance is greater than the fourth distance.

Method of forming guard ring and circuit device

A circuit includes: a first swing reduction circuit coupled between an input/output pad and a buffer circuit, and a second swing reduction circuit coupled between the input/output pad and the buffer circuit. The first swing reduction circuit comprises a first transistor gated by a first bias voltage and comprises a second transistor drained by the first bias voltage. The first swing reduction circuit is configured to increase a voltage at a first node in the buffer circuit when a voltage applied on the input/output pad is equal to a first supply voltage. The second swing reduction circuit is configured to reduce a voltage at a second node in the buffer circuit when the voltage applied on the input/output pad is equal to a second supply voltage.

Temperature instability-aware circuit

A circuit includes a first inverter and a second inverter. The first inverter is coupled to an input terminal. The input terminal receives an input signal varying in a first voltage domain. The second inverter is coupled between the first inverter and an output terminal. The second inverter generates an output signal varying in a second voltage domain. The first inverter includes a first PMOS transistor and a first NMOS transistor. The first PMOS transistor is biased by a first input tracking signal generated from the input signal. The first input tracking signal varies in a third voltage domain. The first NMOS transistor is biased by a second input tracking signal generated from the input signal. The second input tracking signal varies in the second voltage domain.

Buffer circuit between different voltage domains

An electrostatic discharge (ESD) protection circuit (for a protected device in a semiconductor system, the protected device being coupled between a first node and a first reference voltage) includes: an ESD device coupled between the first node and the first reference voltage; a logic block including a first input and an output, the first input being coupled to a second reference voltage, and the output being coupled to an input of the ESD device and a feedback control circuit coupled between the first node and a second input of the logic block.

A buffer circuit includes an input terminal, an output terminal, a buffer, and an RC circuit coupled in series with the buffer between the input terminal and the output terminal. The RC circuit is configured to increase a transition time between logical voltage levels of an output signal generated at the output terminal relative to a transition time between logical voltage levels of an input signal received at the input terminal, and the transition time of the output signal is based on a duration of a logic inversion of the input signal.

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Kaohsiung, Taiwan

Wan-Yen Lin