Skhynix Inc.

Wan Sup Shin

Ki Hong Lee

Jae Jung Lee

Young Geun Jang

Seung Wook Ryu

Sung Soon Kim

Min Sung Ko

Young Ho Yang

Jong Gi Kim

Hee Soo Kim

Chang Soo Lee

Heung Ju Lee

Jun Seok Oh

A method for fabricating a vertical semiconductor device may include forming a lower-level stack including a source sacrificial layer over a semiconductor substrate; forming an upper-level stack including dielectric layers and sacrificial layers over the lower-level stack; forming a vertical channel structure including a channel layer that penetrates the upper-level stack and the lower-level stack; forming a slit that penetrates the upper-level stack while exposing the source sacrificial layer; forming a lateral recess that extends from the slit by removing the source sacrificial layer; forming a first contact layer which is coupled to a portion of the channel layer while filling the lateral recess; selectively forming a second contact layer over an exposed surface of the first contact layer; and selectively forming a chemical barrier layer over the second contact layer.

Vertical semiconductor device and method for fabricating the same

A semiconductor device, and method of manufacturing a semiconductor device, includes second conductive patterns separated from each other above a first stack structure which is penetrated by first channel structures and enclosing second channel structures coupled to the first channel structures, respectively. Each of the second conductive patterns includes electrode portions stacked in a first direction and at least one connecting portion extending in the first direction to be coupled to the electrode portions.

Semiconductor device and manufacturing method of the semiconductor device

A semiconductor memory device includes: a conductive line stack including a plurality of first conductive lines that are stacked over a substrate in a direction perpendicular to a surface of the substrate; conductive pads extending laterally from edge portions of the first conductive lines, respectively; and contact plugs coupled to the conductive pads, respectively.

Semiconductor memory device

A semiconductor device, and a method of manufacturing the semiconductor device, the method includes forming a first stack structure penetrated by first channel structures, forming electrode patterns surrounding second channel structures and separated from each other by first slits and second slits, the second channel structures coupled to the first channel structures, and the second slits comprising a different width from the first slits, filling each of the first slits and the second slits with an insulating material to cover sidewalk of the electrode patterns, and forming third slits passing through the insulating material in each of the second slits and extending to pass through the first stack structure.

A semiconductor device includes a source structure, a bit line, a stacked structure between the source structure and the bit line, a source contact structure penetrating the stacked structure and electrically coupled to the source structure, and a protective pattern interposed between the source contact structure and the source structure and having a varying thickness depending on an area of the protective pattern.

Semiconductor device and manufacturing method of semiconductor device

A semiconductor device, and a method of manufacturing the semiconductor device, the method includes forming a first stack structure penetrated by first channel structures, forming electrode patterns surrounding second channel structures and separated from each other by first slits and second slits, the second channel structures coupled to the first channel structures, and the second slits comprising a different width from the first slits, filling each of the first slits and the second slits with an insulating material to cover sidewalls of the electrode patterns, and forming third slits passing through the insulating material in each of the second slits and extending to pass through the first stack structure.

In an embodiment, the semiconductor device may include interlayer insulating layers, conductive patterns, a channel layer, cell blocking insulating layers, dummy blocking insulating layers, and a data storage layer. The interlayer insulating layers and conductive patterns may be alternately stacked. The channel layer may pass through the interlayer insulating layers and the conductive patterns. The cell blocking insulating layers may be respectively arranged between the channel layer and the conductive patterns. The dummy blocking insulating layers may be respectively arranged between the channel layer and the interlayer insulating layers, and may protrude further toward a side wall of the channel layer than the cell blocking insulating layers. The data storage layer may surround the side wall of the channel layer, and may be formed on a concavo-convex structure defined by the cell blocking insulating layers and the dummy blocking insulating layers.

Semiconductor device and method of manufacturing the same

A semiconductor device includes a stacked structure, openings passing through stacked structure, semiconductor patterns formed over inner walls of the openings, liner layers formed in the openings over the semiconductor patterns, and gap-fill insulating layers formed over the liner layers to fill the openings, wherein each of the gap-fill insulating layers seals an upper portion of the opening and includes at least one air gap.

Semiconductor device and method of fabricating the same

A semiconductor device includes stacked structure, openings passing through stacked structure, semiconductor patterns formed over inner walls of the openings, liner layers formed in the openings over the semiconductor patterns, and gap-fill insulating layers formed over the liner layers to fill the openings, wherein each of the gap-fill insulating layers seals an upper portion of the opening and includes at least one air gap.

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Seongnam-si, South Korea

Wan Sup Shin