Samsung Electronics Co., Ltd.

Wan-Soo Choi

Young Wook Kim

Jinwoo Kim

Dong Eun Shin

Yong Chan Jo

Hyun Jin Choi

Jinwoo Jung

Min-Woo Kim

Jun-Ho Jang

Kui-Yon Mun

Young Woo Jung

Young-Wook Kim

Jun-Seok Park

Bong-Gwan Seol

Byungjune Song

Heetak Shin

Woonjae Chung

Jae-Hwa Lee

Yu-Hun Jun

Won-Jin Lim

Taec-Jun Kim

Hee-tak Shin

Sang-Wook Nam

Sanghoon Yoo

Yonghwan Song

Do Hyeon Park

Hyun Seon Park

Eun-Ju Park

Hee Yeon Tak

A memory storage device is provided. The memory storage device includes: a memory device including a plurality of blocks, the plurality of blocks including a first block which includes a plurality of sub-blocks; and a memory controller configured to, based on use amount differences among the plurality of sub-blocks being greater than a threshold value, increase a use amount of a low use sub-block that has a small use amount from among the plurality of sub-blocks of the first block. The plurality of sub-blocks of the respective blocks are stacked in a direction perpendicular to a substrate of the memory device.

Memory storage device and wear leveling method thereof

A storage device includes an input stage receiving a first command, a queue manager allocating a first queue entry for the first command, a pre-processor storing the first command in the first queue entry and updating a task list with the first command and a core executing the first command in accordance with an order specified in the updated task list. At least one of the queue manager and the pre-processor is implemented in a customized logic circuit.

Storage device with reduced communication overhead using hardware logic

A method for operating a memory controller, the method including: receiving a first command from a first host; storing the first command in a queue; when the first command has a higher priority than a second command currently being performed, pausing an operation of the second command and performing a read operation of the first command; and continuing the operation of the second command after completion of the read operation of the first command.

Method of operating a memory controller in which commands are stored in urgent or normal queues based on priority. a nonvolatile memory device including a buffer selector and a storage device thereof

A method of operating a storage device including a non-volatile memory and a multi-core processor with at least two cores includes the following steps: receiving, by a host interface of the storage device, a first command from a host for requesting the non-volatile memory to perform a predetermined memory operation; generating, by a task scheduler of the storage device, first and second tasks from the first memory command; selecting, by the task scheduler, a first core from among the at least two cores based on execution times of the at least two cores; assigning, by the task scheduler, the first and second tasks to the first core; and requesting, by the first core, a subsequent task from the scheduler while the first core processes the first assigned task and loads code for processing the second task.

Storage device with task scheduler and method for operating the device

A method of operating a multi-bank storage device includes transmitting a write command including stream identification information to the multi-bank storage device, and allocating at least one bank, in which data associated with the write command is to be stored, from among a plurality of banks in the multi-bank storage device, based on striping size information included within the stream identification information. Upon allocation, the data is written into the allocated at least one bank.

Memory systems and methods that allocate memory banks using striping size and stream identification information contained within directive commands

An operation method of an electronic device including a core includes reading first status information from a first status register of a first functional block driven independently of the core, reading second status information from a second status register of a second functional block driven independently of the core, reading first change information from a first flag register of the first functional block, reading second change information from a second flag register of the second functional block, determining whether an operation status of the electronic device is any one status of an idle status and a busy status, based on the read first and second status information and the read first and second change information, and operating in an operation mode corresponding to the determined operation status.

Electronic device and operation method thereof

An operating method of a storage device which includes a plurality of banks includes receiving a write command including stream identification information from a host, allocating a bank, in which data are to be stored, from among the plurality of banks based on a striping size corresponding to the stream identification information, in response to the write command, and writing the data in the allocated bank.

A method of controlling memory devices of a memory controller, the memory devices including a plurality of memory dies, includes receiving at least one data operation request and a power budget from external of the memory controller; determining respective data operation times of the plurality of memory dies, wherein a power consumption due to at least one data operation in response to the at least one data operation request may be equal to or less than the power budget; and controlling the plurality of memory dies based on the data operation times.

Memory controller and storage device including the same

A program method of a multi-bit memory device is provided. First page data is programmed in a first region of a memory cell array. The first page data is stored in a first buffer of a page buffer. Second page data is programmed in the first region of the memory cell array. The second page data is stored in a third buffer of the page buffer. Third page data is stored in the first region of the memory cell array. The second page data stored in the third buffer is transferred to a second buffer of the page buffer and the third page data is stored in the third buffer. The first to third page data stored in page buffer are programmed in a second region of the memory cell array.

Multi-bit memory device and on-chip buffered program method thereof

A method of operating a storage device comprises copying first valid pages in a first block into a first latch unit based on a first volatile memory device, the first block being set on multiple nonvolatile memory devices, copying second valid pages in the first block into a second latch unit based on the first volatile memory device, and copying the first valid pages in the first latch unit and the second valid pages in the second latch unit into a second block, the second block being set on the nonvolatile memory devices and being different from the first block.

Storage device comprising volatile and nonvolatile memory devices, and related methods of operation

According to example embodiments, a table management method includes determining whether a table associated with a page in at least one nonvolatile memory device needs to be recovered, performing a block scan operation on a block in the at least one nonvolatile memory device if the table needs to be recovered, recovering the table using a time difference read from each of a plurality of pages in the block during the block scan operation, and updating the recovered table to the at least one nonvolatile memory device. The table is associated with a page among the plurality of pages in the block. The time difference is time elapsed until a current page is programmed from program time of a previous page among the plurality of pages.

Storage device and table management method thereof

A user device includes a storage device including a flash memory; and a host connected to the storage device via an interface and adapted to transmit data to the storage device. The host provides the storage device with erase count information of the flash memory using a host flash translation layer (FTL), provides the storage device with reprogram information when the flash memory uses a reprogram method, or provides the storage device with page offset information of an open block of the flash memory.

User device having a host flash translation layer (FTL), a method for transferring an erase count thereof, a method for transferring reprogram information thereof, and a method for transferring a page offset of an open block thereof

A storage device is provided which includes a plurality of memory chips each nonvolatile memory cells divided into a first memory region and a second memory region; and a memory controller configured to buffer data provided from the exterior and to control the plurality of memory chips to perform a buffer-program operation and a main-program operation. The buffered data is stored at the first memory region at the buffer-program operation and data stored at the first memory region is written at the second memory region at the main-program operation. During a main-program operation of a first memory chip among the plurality of memory chips, the memory controller buffers data to be written at a second memory chip.

Data storage device comprising nonvolatile memory chips and control method thereof

In one embodiment, a memory system includes a memory device with a first memory and a second memory, and a controller configured to control storing of data in the memory device. The controller is configured to control an (N&#x2212;1)piece of meta data to be stored in the second memory when an Npiece of user data is stored in the first memory or control the Npiece of the user data to be stored in the second memory when the (N&#x2212;1)piece of the meta data is stored in the first memory, where N denotes a natural number equal to or greater than '1'. Also, a time period of storing the Npiece of the user data is controlled to partially or entirely overlap with a time period of storing the (N&#x2212;1)piece of the meta data.

Growing community of inventors

Hwaseong-si, South Korea

Wan-Soo Choi