International Business Machines Corporation

Wan Lin Leung

Thomas Basilio Genduso

Richard Allen Kelley

John K Langgood

Douglas R Chisholm

Patrick M Gannon

Timothy R Marchini

James T Moyer

Mark C Snedaker

Robert G Iseminger

Henry W Adams, Iii

John Joseph Szarek

Henry R Brandt

Kimberly Kibbe Sendlein

Frank Cassatt Harwood

Edward Yee

Dieu Huynh

Leslie F McDermott

Gerald George Isaac

A method and system in a superscalar data processing system are disclosed for the efficient processing of an instruction by moving only pointers to data. Multiple instructions in the superscalar data processing system are processed during a single clock cycle. A determination is made whether one of these instructions is a particular type of instruction which specifies data to be moved or copied from a logical origination location to a logical destination location during processing of the instruction. In response to a determination that the instruction is a particular type of instruction, a first pointer field is established associated with the instruction for associating a pointer stored in the first pointer field with the logical origination location. A second pointer field is also established associated with the instruction for associating a pointer stored in the second pointer field with the logical destination location. A first pointer is associated with the instruction and identifies a physical location wherein the data is stored. In response to the first pointer being stored in the first pointer field, the logical destination location is associated with the physical location. The instruction is processed by storing the first pointer in the second pointer field. The logical destination location becomes associated with the physical location, such that the data remains in its original physical location during processing of the instruction.

Method and system in a superscalar data processing system for the efficient processing of an instruction by moving only pointers to data

Bus interface units interposed between a multiple processor bus and individually coupled to the respective processors in a complex incorporating a multitude of processors, where each bus interface unit includes block snoop control registers responsive to signals from a system memory controller including enhanced function supportive of I/O devices with and without block snooping compatibility. The BIU provides functionality for the bus of the multiple processors to be processor independent. This architecture reduces the number of snoop cycles which must access the processor bus, thereby effectively increasing the available processor bus bandwidth. This in turn effectively increases overall system performance.

Snooping a variable number of cache addresses in a multiple processor system by a single snoop request

A mechanism is provided for supporting stack cache memory device management of POP read or PUSH write data in a computer system. The computer system further comprises a main memory and a processor associated with the stack cache memory device. The stack cache memory device includes at least one cache line having a plurality of address spaces arranged from a lowest address to a highest address. In response to the processor initiating a POP read or PUSH write operation, the mechanism provides logic for preventing placement of data in the cache which will not be reused by the processor, and for further preventing removal of data which may be reused by the processor.

Cache memory storage space management system and method

A method and system in a superscalar data processing system are disclosed for the temporary designation and utilization of a plurality of physical registers as a stack. For each of the multiple instructions to be processed during a single clock cycle by the data processing system, a determination is made whether each of the instructions is a particular type of instruction. If a determination is made that an instruction is a particular type of instruction, a quantity of physical registers to be temporarily designated as a stack is determined utilizing the instruction. A second plurality of physical registers available to be utilized as a stack are determined whether the second plurality of the quantity. The second plurality of physical registers are then temporarily designated and utilized as a stack.

Method and system for the temporary designation and utilization of a

A method and system in a superscalar data processing system are disclosed for the temporary designation of a physical register as a particular general register. The data processing system is capable of processing multiple instructions during a single clock cycle. Physical registers are established. None of the physical registers are initially designated as a particular general register. No general registers exist which are initially designated as particular general registers. For each of the multiple instructions, a determination is made as to whether the instruction is a load register instruction. If the instruction is a load register instruction, a determination is made as to whether the instruction is associated with a logical register name. Each one of the logical register names identifies a different general register. In response to the instruction being associated with a logical register name which identifies a particular general register, one of the physical registers is temporarily designated as the general register which is identified by the logical register name associated with the instruction. A special instruction register is established for each of the multiple instructions. Each special instruction register includes a plurality of fields including an allocation field. A first indicator is stored in the allocation field for special instruction registers associated with load instructions. A second indicator is stored in the allocation field for special instruction registers which are not associated with load instructions.

Special instruction register including allocation field utilized for

A memory controller having request queue and snoop tables is provided for functioning with bus interface units interposed between a multiple processor bus and individually coupled to the respective processors in a complex incorporating a multitude of processors, where each bus interface unit includes block snoop control registers responsive to signals from a system memory controller including enhanced function supportive of I/O devices with and without block snooping compatibility. The tables are compared to minimize and more efficiently institute snoop operations as a function of the presence or absence of the same listings in the tables. The BIU provides functionality for the bus of the multiple processors to be processor independent. This architecture reduces the number of snoop cycles which must access the processor bus, thereby effectively increasing the available processor bus bandwidth. This in turn effectively increases overall system performance.

System for executing I/O request when an I/O request queue entry matches

Snooping a variable number of cache addresses in a multiple processor

A stack cache memory mechanism and method for managing the mechanism are provided. The mechanism comprises a data array including a plurality of storage elements in which stack data may be stored, and a plurality of individual stack tag sets for identifying beginning and ending locations of a corresponding plurality of individual stacks contained within the data array. Each of the individual stack tag sets comprise (i) a first register for containing an address in the data array corresponding to the top of a stack associated with that individual stack tag set and (ii) a second register for containing an address in the data array corresponding to the bottom of a stack associated with that individual stack tag set. A backward pointer array comprises a plurality of backward pointers which map each of the plurality of stack tag sets to address locations in the data array. Allocation logic determines which of the data array storage elements are currently included within existing stacks, as defined by the plurality of backward pointers and the plurality of stack tag sets, and which of the data array storage elements are available to be allocated to a stack.

System and method for allocating cache memory storage space

A computer system that has a main memory and a writeback cache memory also has an I/O device capable of data streaming. A memory controller responds to signals that the I/O device will perform a burst transfer of data to the main memory and blocks potential writebacks from the cache memory to the I/O device. Potential writing over of the data from the I/O device by a flushed cache line written back to the main memory is thereby prevented. The system performance is increased since the data from the I/O device can be written to the main memory without waiting for a snoop cycle and a writeback to be performed.

Computer system with a device for selectively blocking writebacks of

In a computer system having a central processing unit (CPU) in circuit communication with a memory via a memory bus and having first and second peripheral bus controllers generating first and second dissimilar peripheral buses, a multibus arbiter is provided for arbitrating access of a memory bus between the two dissimilar buses. The multibus arbiter has an assignment register, a time slot pointer, and an arbitration circuit. The length of the assignment register and time slot pointer controls the granularity of control of accesses to the memory bus by the peripheral buses. The assignment register holds a multibit assignment value that determines which of the two peripheral buses will be given access to the memory bus for a given time slot during contention. The time slot pointer selects one of the bits of the assignment register and points to a different bit responsive to both peripheral buses requesting access to the memory bus at the same time and one of said peripheral bus arbiters indicating that the current access of the memory bus is complete.

Method and apparatus for bus arbitration in a multiple bus information

A local processor is connected to one port of a dual port memory controller. A bus having a BURST signal line is connected to the other port. The memory controller controls access to a local memory. A remote processor can perform a semaphore operation on a semaphore stored in the local memory by translating a LOCK signal from the remote processor into a bus BURST signal that is activated for a period allowing the remote processor to read and modify the semaphore. While the semaphore operation is being performed, the local processor can access the local memory.

Data processing system and memory controller for lock semaphore

In a computer system, a plurality of input/output processors (IOP's) are connected via an asynchronous input/output bus, called an 'SPD' bus, to one side of an input/output interface controller (IOIC). The other side of the IOIC is connected to a storage controller (SC) via a synchronous bus called an 'adapter' bus. The SC is connected to a common system memory and possibly also to an instruction processing unit. The IOIC comprises at least one shared DMA facility for executing DMA read/write storage operations requested by the IOP's via the SPD bus. Each shared DMA facility includes a buffer for holding control information and data to be transmitted between the SC and one of the IOP's. This enables the SPD bus to be released for utilization by otehr IOP's connected thereto during periods of 'storage latency' that occur after a DMA storage operation has been initiated by one IOP.

Method and apparatus for increasing system throughput via an

A unique high-speed hardware arrangement for generating double-level address translations in combination a translation look-aside buffer (TLB) structure that can store and lookup intermediate translations during a double-level translation. The hardware proceeds to the completion of a double-level translation without having to backup its operation, although an intermediate TLB miss is encountered, without danger of CPU deadlock occurring. The hardware arrangement also performs all single-level address translations required by the system.

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Raleigh, NC, United States of America

Wan Lin Leung