Sk Keyfoundry Inc.

Wan-Chul Kong

Keesik Ahn

Sungbum Park

Seongjun Park

Woojin Han

Changbum Im

Ilwoo Lee

An eFuse one-time programmable (OTP) memory includes an eFuse intellectual property (IP) configured to perform one-time writing and multiple readings for a plurality of memory cells, and a serial interface (SI) logic configured to receive a clock signal and a trim signal from a master device, and perform data writing to, or reading from, the eFuse IP based on the clock signal and the trim signal. The trim signal includes a start signal, a mode signal configured for a write mode or a read mode, and control signals configured to read or write for each of a plurality of addresses corresponding to the plurality of memory cells.

eFuse OTP memory device including serial interface logic and operation method thereof

A low-power retention flip-flop is provided. The low-power retention flip-flop may include: a master latch configured to output an input signal based on first control signals; a slave latch configured to output the signal from the master latch based on second control signals; and a control logic configured to generate the first control signals based on a clock signal, and provide the generated first control signals to the master latch, and generate the second control signals based on the clock signal and a power down mode signal, and provide the generated second control signals to the slave latch.

Low-power retention flip-flop

An eFuse one-time programmable (OTP) memory is provided. The eFuse OTP memory supports inter integrated circuit (I2C) communication, and an operation method thereof. The eFuse OTP memory includes: an eFuse intellectual property (IP) which data writes once and data reads multiple times for a plurality of addresses; and an I2C slave which communicates with an I2C master based on a serial clock line and a serial data line, and performs the data write and the data read to and from the eFuse IP.

Growing community of inventors

Gwangju-si, South Korea

Wan-Chul Kong