Intel Corporation

Infineon Technologies Ag

Walther Lutz

Erwin Ruderer

Georg Seidemann

Peter Baumgartner

Martin Ostermayr

Joachim Assenmacher

Richard Geiger

Georgios Panagopoulos

Bernhard Dobler

Roswitha Deppe

Richard Hudeczek

Johannes Xaver Rauh

Carla Moran Guizan

Alexander Bechtold

Roshini Sachithanandan

IC devices including transmission lines are disclosed. An example IC device includes two electrically conductive layers (first and second layers) and a support structure between the two electrically conductive layers. The first layer is coupled to transistors over or at least partially in the support structure. A shield of a transmission is placed in the first layer. Conductors of the transmission line are placed in the second layer and are coupled to the first layer by TSVs. Another example IC device includes three electrically conductive layers (first, second, and third layers). The first layer is coupled to transistors over or at least partially in the support structure. A shield of a transmission line is placed in the second layer and conductors of the transmission line are placed in the third layer. The conductors are coupled to the first layer by TSVs and coupled to the second layer by vias.

Integrated circuit device comprising tunable transmission line using buried power rail technology

A semiconductor die is disclosed, including a plurality of transistors at a frontside of a semiconductor substrate, a backside inductor at a backside of the semiconductor substrate; and a frontside inductor at the frontside of the semiconductor substrate. The frontside inductor and the backside inductor are inductively coupled.

Semiconductor dies and devices with frontside and backside coils for inductive coupling

A semiconductor die is disclosed, including circuitry comprising a transistor at a frontside of a semiconductor substrate, and a backside inductor at a backside of the semiconductor substrate. The backside inductor is electrically connected to the transistor of the circuitry.

Semiconductor dies and devices with a coil for inductive coupling

Implementations are presented herein that relate to a standard cell including a measuring structure for controlling process parameters during manufacture of an integrated circuit. A standard cell is formed in a plurality of material layers of an integrated circuit to perform part of a function of the integrated circuit, wherein the plurality of material layers is configured to be patterned by a plurality of mask layers during manufacture of the integrated circuit, wherein the standard cell includes a measuring structure that is placed within boundaries of the standard cell, wherein the measuring structure includes at least one feature in at least one of the plurality of material layers and the plurality of mask layers, wherein the at least one feature is configured to provide measurement results in order to control process parameters during manufacture of one of the material layers and mask layers.

Measurement structure in a standard cell for controlling process parameters during manufacturing of an integrated circuit

A process of manufacturing a semiconductor circuit includes providing a substrate layer, forming a metal layer above the substrate layer, incorporating circuit components in the substrate layer, and electrically connecting the circuit components to the metal layer. The process includes configuring the circuit components to perform an electrical function of the semiconductor circuit. The semiconductor circuit has a specific electrical conductivity between the substrate layer and the metal layer based on the electrical function performed. The process includes increasing the electrical conductivity between the substrate layer and the metal layer compared with the specific electrical conductivity.

Manufacturing semiconductor circuit, corresponding semiconductor circuit, and associated design process

A multi-pass method for designing at least a portion of a circuit layout on a substrate is provided which includes receiving or generating a first level frame including an electrical component; generating a fill pattern on the first level frame outside of a forbidden area of said first level frame; generating a next level frame, the next level frame including the first level frame and a next level fill area outside of the first level frame; and adding a conductor to the next level frame. The conductor is connected to the electrical component, a first portion of the conductor is in the first level frame and a second portion of the conductor is in the next level fill area. The method includes generating a next fill pattern on the next level fill area outside of a forbidden area of said next level fill area, modifying the first level forbidden area to extend at least over the electrical component and the first portion of the conductor, and removing any of the plurality of structures in the fill pattern that are within the modified first level forbidden area.

Growing community of inventors

Erding, Germany

Walther Lutz