Bell Telephone Laboratories

Walter Rosenzweig

Austin C Dumbri

An improved IGFET bootstrap driver circuit capable of driving a load impedance to substantially full VDD power supply voltage and holding the load at that voltage for an indefinite period of time. The circuit includes a load transistor, a feedback capacitor connected between the source and gate electrodes of the load transistor, a fix valued resistor connected between the gate electrode of the load transistor and an on-chip bias voltage generating circuit for providing a bias voltage greater than VDD+VT. The resistor and the bias voltage generating circuit provide sufficient current to replenish the charge lost from the feedback capacitor through junction leakage currents in the driver circuit. The resistor is of a sufficiently high value such that the current drain from the generating circuit is insignificantly small in comparison to the current drain from the VDD power supply. The improved circuit also permits the load transistor to be switched 'on' or 'off' by an externally applied signal.

IGFET Bootstrap circuit

A back gate bias voltage generator circuit consists of three MOS transistors (Q4, Q5, Q6) with a separate load element (Q1, Q2, Q3) coupled to the drain of each and a voltage clamp (Q7) connected to an output terminal (16). A terminal at the potential of a power supply (VCC) serves as one input and a terminal at the substrate potential (VSub) serves as another input. When the power supply (VCC) potential and the substrate potential are within normal operating ranges, the output terminal (16) assumes a reference potential (VSS). The potential of the output terminal increases in magnitude if either of the two input potentials (VSS, VSub) goes outside preselected operating ranges.

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Allentown, PA, United States of America

Walter Rosenzweig