Motorola Corporation

National Semiconductor Corporation

Walter R Davis

David L Cave

Tim D Isbell

Daniel D Culmer

Harry J Bittner

Tim W Henry

A circuit for pulse width modulating the output of a voltage controlled oscillator without introducing any ocillator frequency or amplitude (slope) modulation. A summing circuit is combined with a comparator and provided with inputs that accommodate differential sum/difference inputs, an error input and a ramp input from the oscillator or other source. The ramp and error signals are combined differentially to pulse width modulate the comparator output and pulse width modulation can also be achieved by via the sum/difference inputs a differential relationship.

Pulse width modulator circuit for switching regulators

A circuit is shown for pulse width modulating the output of a voltage controlled oscillator without introducing any oscillator frequency or amplitude (slope) modulation. A summing circuit is combined with a comparator and provided with inputs that accommodate differential sum/difference inputs, an error input and a ramp input from the oscillator or other source. The ramp and error signals are combined differentially to pulse width modulate the comparator output and pulse width modulation can also be achieved via the sum/difference inputs in a differential relationship.

A totem pole output stage is shown where current spikes are minimized. The circuit disclosed employs four transistors and three diodes to eliminate the spikes associated with the input low to high transition. A fourth diode minimizes the input high to low transition time.

Totem pole output circuit with reduced current spikes

A linear amplifier output stage is provided with unity gain buffer means having an input coupled to the output terminal and an output coupled to the stage input. The unity gain buffer means is normally turned off by a control signal. When the amplifier is disabled by switching its bias current off, the buffers are turned on so that the output stage input capacitance is charged or discharged via the buffer means in accordance with the output terminal signal. When a plurality of such amplifiers are commonly coupled to a signal line the off amplifiers cannot be driven into conduction by the operating amplifier's output signal.

Bistate linear amplifier circuit

A switching regulator is provided with a separate or isolated d-c output for operating the switching pulse generating circuits. A large value resistor coupled between the d-c input line and the isolated d-c output will charge the filter capacitor to a higher than normal voltage. A zener diode string is coupled across the filter capacitor. The zener diodes in combination have a higher than nominal zener voltage. The diodes will respond to the capacitor voltage and develop a starting pulse that initiates the power supply when it is first energized.

Switching regulator off-line starting circuit

An amplifier circuit is disclosed which utilizes a differential-to-single ended converter having a floating current mirror. The amplifier includes a differential driving circuit having first and second differential output terminals which are respectively connected to first and second current supplies and an output transistor. The current mirror includes a diode-connected transistor having a base-to-emitter junction connected in parallel with the base-to-emitter junction of a further transistor. The base electrode of the diode-connected transistor is connected to one of the differential output terminals and the collector electrode of the further transistor is connected to the other differential output terminal. The emitter electrodes of the diode-connected transistor and of the further transistor are adapted to receive a voltage having a fixed magnitude which enables the transistors of the current mirror to have the same conductivity type as the transistors of the differential driving circuit and the output transistor.

Floating NPN current mirror

The amplifier configuration includes a double-to-single ended converter having two interconnected portions, each having three signal paths. Two of the signal paths include transistors of a first conductivity type having main electrodes coupled between one of the output terminals of a differential amplifier and a power supply conductor. The other path includes a transistor of the second conductivity type having a control electrode coupled to one of the differential amplifier output terminals and main electrodes coupled between power supply conductors. Identical current sources drive corresponding transistors of each portion. The transistors of the second conductivity type enable quiescent voltages of only one base-to-emitter voltage drop to be developed at each of the output terminals of a differential amplifier to facilitate balance and maximization of the dynamic signal range. The substantially identical configurations of the two portions of the converter enable substantially identical quiescent currents to be drawn thereby to minimize the differential amplifier input offset voltage.

Monolithic amplifier having a balanced, double-to-single ended converter

A stabilizing circuit which increases the effective value of a capacitor and the structure of a monolithic capacitor are disclosed. The stabilizing circuit includes a transistor having a base electrode connected to the capacitor and an emitter electrode connected to a point at which it is desired to provide an increased effective capacitance. The capacitor structure is suitable for being included in monolithic integrated circuits having diffused isolation regions. A first plate of the capacitor is formed by a metallization layer, the second plate of the capacitor may be formed by an emitter diffusion into the isolation diffusion. A base diffusion which is conductively connected to the emitter diffusion and to the isolation diffusion facilitates connection of the second plate of the capacitor to the substrate.

Capacitor structure and circuit facilitating increased frequency

A current limit circuit is disclosed for sensing the current drain of a load connected in series therewith. Under normal operating conditions the circuit presents a relatively low impedance in series with the load. Circuit overload protection is provided if the current increases above a predetermined value by a current limiting circuit provided for limiting the current conducted therethrough. In response to the current limiting condition, thermal shutdown of the circuit occurs to reduce the current that is supplied to the load to a predetermined minimum value i.e., the current limit circuit presents an impedance to the load which is relatively much greater than the impedance of the current limit circuit during normal operating conditions. After a predetermined time, the current limit circuit is again rendered operative and if the circuit overload condition is still present the aforedescribed cycle is repeated until the fault condition is corrected.

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Sunnyvale, CA, United States of America

Walter R Davis