International Business Machines Corporation

Walter Pietschmann

Steven R Carlough

Gary A Van Huben

Susan M Eickhoff

Markus Cebulla

Logan I Friedman

Nicholas Steven Rolfe

Patrick James Meaney

Juergen Koehl

Joerg H Walter

Norbert Schumacher

Volker Urban

Juergen Saalmueller

Herbert Meyerdirks

A memory system, architecture, and method for storing data in response to commands received from a host is disclosed. The memory system includes a memory control circuit configured to receive commands from the host; at least one memory device configured to store data; and at least one data buffer circuit associated with the at least one memory device and the memory control circuit, the data buffer circuit having data buffers and at least one register. The system preferably includes communication links between the host, the at least one memory control circuit, the at least one data buffer circuit, and the at least one memory device. The system preferably is configured so that register access commands are sent by the host to the memory control circuit over the communication links between the host and the memory control circuit.

Register access in a distributed memory buffer system

A method, apparatus and system testing a plurality of semiconductor chips in a distributed memory buffer system is provided. Embodiments of the present invention recognize improvements to testing signals through the chip substrate and motherboard. This invention overloads the shared broadcast bus by using it for test purposes rather than its normal mainline function. One of the main components of this invention is the A/C chip. In test mode, the AC chip converts JTAG commands into an internal test format and sends test data over the shared broadcast bus. Each data chip determines whether the scan data is for itself or if it should ignore it. The corresponding data chip then processes the data, and if necessary sends return data back to the address and command chip, where it is converted back into JTAG format and can be seen by the tester.

JTAG support over a broadcast bus in a distributed memory buffer system

The present invention relates to a method for validating the correct logical function and timing behavior of a digital circuit design within a cycle-based verification environment. The method comprises the steps of providing a VHDL description of the digital circuit design, performing a logic synthesis, wherein the VHDL description is turned into a design implementation in terms of logic gates, and creating a netlist including the elements of the digital circuit design and the connections between said elements. The method comprises the further steps of providing a transformation script with at least one transparent storage element, wherein said transparent storage element represents a path delay within the digital circuit design, creating a new netlist with the at least one transparent storage elements, running a verification, and checking if the new netlist is clean from a logical and timing point of view.

Method for validating logical function and timing behavior of a digital circuit decision

A system for supplying power to an apparatus (170, 175) with a power-storage device (200) for storing electric power, a first measuring device (310) for measuring a first electrical quantity of the power-storage device (200), a time-determining device (360) for determining the time taken for the first electrical quantity to reach a first level, a second measuring device (320) for measuring a second electrical quantity of the power-storage device (200) and a comparator (330) for comparing the second electrical quantity relative to the determined time with a stored typical time-characteristic of the second electrical quantity. Thereby a method of assessing the lifetime and capacity of the power-storage device (200) is used with as a first step (500) the measurement of a first electrical quantity of the power-storage device (200), as a second step (510) the determination of the time taken for the first electrical quantity to reach a first level, as a third step (520) the measurement of a second electrical quantity of the power-storage device (200), as a fourth step (530) the comparison of the second electrical quantity relative to the determined time with a stored typical time-characteristic of the second electrical quantity and as a fifth step (540) the evaluation of the comparison from the fourth step for an assessment of the lifetime and capacity of the power-storage device (200).

System for supplying power to an apparatus and method for the assessment

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Horb-Bittelbronn, Germany

Walter Pietschmann