Intel Corporation

Other

Walter P Hays

Michael J Keith

David L Sprague

Kevin Harney

Allen H Simon

Eiichi Kowashi

George F Salem

Vitaly H Shilman

Shih-Wei Shiue

Anthony P Bertapelli

Gregory M Papadopoulos

Michael Papadopoulos

Anthony P Bertapellil

A system and method for arbitrating among memory requests. According to a preferred embodiment, the system comprises a global memory and a plurality of datapaths. Each datapath comprises a datapath processor for executing instructions of an instruction sequence and for providing a plurality of memory request signal types in accordance with the instructions, wherein the plurality of memory request signal types comprises instruction memory request signals, scalar memory request signals, first-in and first-out memory request signals, statistical decoder memory request signals, and block transfer memory request signals. Each datapath also comprises local memory, a global port for transferring data between the local memory and the global memory, and a dual port comprising first and second local ports for transferring data between the local memory and the datapath processor, wherein the first and second local ports permit simultaneous transfer of data between the local memory and the datapath processor. The system comprises a data bus coupled to the global memory for transferring data to and from the global memory, and a transfer controller for controlling block transfer and scalar data transfers between the local memory and the global memory over the data bus and for arbitrating among competing datapaths of the plurality of datapaths to grant to a selected datapath access to the data bus in accordance with the signal types of the memory request signals generated by datapaths of the plurality of datapaths.

System for controlling arbitration using the memory request signal types

A method and apparatus for processing data. According to a preferred embodiment, the apparatus comprises a plurality of datapaths, each datapath comprising datapath processor, and a statistical decoder input channel device. The statistical decoder input channel device prefetches variable length encoded data from a variable length encoded data source in response to a request by a program running on a datapath processor of a datapath of the plurality of datapaths. The statistical decoder input channel device comprises a statistical decoder processor and memory for decoding the variable length encoded data to provide fixed length decoded data, and a transmission output channel for transmitting the fixed length decoded data to the datapath.

System with plurality of datapaths having dual-ported local memory

A system and method for processing data. According to a preferred embodiment, the system comprises a global memory and a plurality of datapaths. Each datapath comprises a datapath processor for executing instructions of an instruction sequence and for providing a plurality of memory request signal types in accordance with the instructions, local memory, a global port for transferring data between the local memory and the global memory, and a dual port comprising first and second local ports for transferring data between the local memory and the datapath processor, wherein the first and second local ports permit simultaneous transfer of data between the local memory and the datapath processor. The system comprises a data bus coupled to the global memory for transferring data to and from the global memory, and a transfer controller for controlling block transfer and scalar data transfers between the local memory and the global memory over the data bus and for arbitrating among competing datapaths of the plurality of datapaths to gram to a selected datapath access to the data bus in accordance with the signal types of the memory request signals generated by datapaths of the plurality of datapaths.

A data processing system having execution units for executing instruction sequences determines at least two conditionals in accordance with the instructions and sets respective flags according to the determined conditionals. These flags are stored and later retrieved sequentially and the execution unit executes selected instructions of the instruction sequence according to the sequentially retrieved mask flags. These masked flags may be stored sequentially in a stack for sequential retrieval at a later time.

Simd with selective idling of individual processors based on stored

A single-instruction multiple-data video signal processor employs a dual-ported local memory architecture in each local memory including a dedicated port for transfers between the local memory and a global memory. A block transfer controller, in combination with the dedicated port, permit each access to the global memory by a datapath processor to be overlapped with its instruction processing, thus usually avoiding stalling of the video signal processor.

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Brookline, MA, United States of America

Walter P Hays