International Business Machines Corporation

Walter Niklaus

Scott Barnett Swaney

Tobias Webel

Dietmar Schmunkamp

Adolf Martens

Michael F Fee

Timothy Gerard McNamara

Stefan Amann

Christopher Raymond Conklin

Ching-Lung L Tong

Ralf Ludewig

Jeffrey A Magee

Linda-Marie Weber

Matthias Lukas Chavanne

A data processing system includes one or more computer systems, each executing at least one hypervisor. Host bus adapters on the computer system are connectable to storage resources in at least one storage area network. The at least one hypervisor provides virtual instances of the host bus adapters as virtual host bus adapters, and a world-wide unique port number and a logical unit number are used to access a storage volume. A globally unique identifier is used to identify the storage volume. The system includes a management server comprising a management instance for evaluating a possibility of attaching storage resources to virtual machine instances generated by the hypervisor.

Attaching storage resources to virtual machine instances

The present invention provides an improved method for updating the settings of a processor or a processor core, respectively, concurrently to the operation of the respective processor system in which the processor or processor core, respectively, is running. This enables the insertion of new scan chain data and thus enabling the modification of the hardware characteristics of the processor.

Updating settings of a processor core concurrently to the operation of a multi core processor system

A digital system and method of operating the same. The system comprises a processor chip including a first elastic interface domain, wherein the first elastic interface domain comprises a first processor X logic and a first processor Y logic, wherein the first processor X and Y logic comprise first X and Y latches, respectively; and a first ASIC chip electrically coupled to the processor chip, wherein the first processor X and Y logics are configured to be simultaneously in a functional mode, wherein the first processor X logic is configured to switch from the functional mode to a scanning mode while the first processor Y logic remains in the functional mode, and wherein in response to the first processor Y logic being in the functional mode, the first processor Y logic is configured to generate a first reference ASIC clock signal to the first ASIC chip.

Generating clock signals for coupled ASIC chips in processor interface with X and Y logic operable in functional and scanning modes

A method for automatic scan completion in the event of a system checkstop in a processor. The processor includes: a processor register; a millicode interface connected between the processor register and a checkstop scan controller; a checkstop logic circuit connected between the checkstop scan controller and a checkstop scan engine; and a scan chain engine and a scan chain connected to the checkstop scan engine. The method includes (a) upon occurrence of a checkstop serially reading data from a processor register and serially writing the data to latches of a scan chain register; and (b) upon occurrence of a system checkstop during (a), stopping the reading and writing and moving data sent before the system checkstop from latches of the scan chain where the data was stored when the system checkstop occurred to latches where the data would have been stored if the system checkstop had not occurred.

Method and apparatus for automatic scan completion in the event of a system checkstop

A computer implemented method and data processing system are provided for preventing firmware defects from disrupting logic clocks. In response to a firmware interface requesting a scan operation for a functional unit, protection logic allows a scan enable to activate to the functional unit only if the logic clocks are stopped to that functional unit, otherwise the scan enable is not activated, an error is indicated, and an interrupt is presented to firmware. Also, in response to a command from a firmware interface to stop the logic clocks to a functional unit, protection logic allows the clocks to be stopped to the functional unit only if the functional unit is already indicating a catastrophic error, otherwise the clocks are not stopped, an error is indicated, and an interrupt is presented to firmware.

Method to prevent firmware defects from disturbing logic clocks to improve system reliability

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Jettingen, Germany

Walter Niklaus