Xilinx, Inc.

Walter N Sze

Stephen M Trimberger

Raymond C Pang

Jennifer Wong

Kameswara K Rao

John M Thendean

Ui Sun Han

Tsu-Chien Shen

Vincent J Jorgensen

Systems and methods are provided for verifying respective configuration data values for programming configuration memory cells of an integrated circuit device such as a programmable logic device (PLD). Each configuration memory cell controls an input of a corresponding initialization value from a file in response to a selectable assertion of an initialization signal of a test bench during a logic simulation of the PLD. The file structurally associates the configuration memory cell with the corresponding initialization value. A current value of one or more of the configuration memory cells is written with the respective configuration data value via a configuration port of the PLD during the logic simulation. Each configuration memory cell compares its initialization and current values in response to a selectable assertion of a check signal of the test bench. A mismatch error is output in response to a difference between the initialization and current values of one or more of the configuration memory cells.

Verifying configuration memory of a programmable logic device

Methods and systems provide for early and simplified testing for defects in the interconnects of a programmable logic device (PLD) and in associated software tools. Data that describes the interconnects are read from a database for the PLD. For each interconnect, a respective test design is automatically generated with the test design replacing a portion of a coupling between an input pad and an output pad in an archetypal test design with a coupling that includes the interconnect. A respective configuration is automatically generated for the PLD from each test design. A respective operation of the PLD programmed with each configuration is simulated, and each operation of the PLD for is checked inconsistency with an expected result. In response to any inconsistency, an indication of the inconsistency is displayed to a user.

System and method for testing of interconnects in a programmable logic device

A method () of reducing a size of a netlist for a target architecture can include the steps of creating () a netlist of objects for the target architecture, identifying () objects specific to the target architecture that are repeated regularly to identify potential dummy objects, creating () a list of objects used by a design in the target architecture, and forming () a list of unused objects in the target architecture from the netlist of objects and the list of objects used by the design. The method can further include the steps of replacing () at least one object in the list of unused objects with an appropriate dummy object to form a modified netlist and simulating () the modified netlist.

Dummy block replacement for logic simulation

It is sometimes desirable to protect a design used in a PLD from being copied. If the design is stored in a different device from the PLD and read into the PLD through a bitstream, an unencrypted bitstream could be observed and copied as it is being loaded. According to the invention, a bitstream for configuring a PLD with an encrypted design includes unencrypted words for controlling loading of the configuration bitstream and encrypted words that actually specify the design.

Bitstream for configuring a PLD with encrypted design data

It is sometimes desirable to protect a design used in a PLD from being copied. According to the present invention, the design is encrypted, then loaded into a PLD, then decrypted, and then loaded into the configuration memory of the PLD. An attacker could relocate the design to a visible part of the PLD and learn the design. The present invention prevents design relocation by attaching address information to the encryption key or by encrypting an address where the design is to be loaded as well as encrypting the design itself. Thus, if an attacker tries to load the design into a different part of the PLD, the encrypted design will not decrypt properly.

Programmable logic device with decryption and structure for preventing design relocation

It is sometimes desirable to encrypt a design for loading into a PLD so that an attacker may not learn and copy the design as it is being copied into the PLD. According to the invention, a method for generating a bitstream for storing an encrypted design begins by generating an unencrypted bitstream including bits representing the design and bits that control loading of the design. The bits representing the design are encrypted and are combined with the bits that control loading, which are not encrypted.

Partially encrypted bitstream method

It is sometimes desirable to protect a design used in a PLD from being copied. If the design is stored in a different device from the PLD and read into the PLD through a bitstream, the design may be encrypted as it is read into the PLD and decrypted within the PLD before being loaded into configuration memory cells for configuring the PLD. According to the invention, in such a device, a method is provided to prevent the design from being read back from the PLD in its decrypted state if it had been encrypted when loaded into the PLD.

Programmable logic device with method of preventing readback

To prevent copying of a design implemented in a programmable logic device (PLD), the PLD itself stores a decryption key or keys loaded by the designer, and includes a decryptor for decrypting an encrypted configuration bitstream as it is loaded into the PLD. The PLD also includes logic for reading header information that indicates whether the bitstream is encrypted, and can accept both encrypted and unencrypted bitstreams. The encryption keys may be stored in non-volatile memory or backed up with a battery so that they are retained when power is removed.

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Saratoga, CA, United States of America

Walter N Sze