Freescale Semiconductor,inc.

Wernher Von Braun Centro De Pesquisas Avancadas

Walter Luis Tercariol

Fernando Zampronho Neto

Sandro A P Haddad

Rafael M Vilela

Jon Scott Choy

Andre Luis Vilas Boas

Ivan Carlos Ribeiro Do Nascimento

Ivan Carlos Ribeiro Nascimento

Henrique Uemura Okada

Alexander Peter Sieh

Fernando Chavez Porras

Richard Saez

Osmar Vieira Machado

Ademir L Xavier

Daniel Vidal

Richard T L Saez

A RFID tag () includes an antenna () that includes a first dipole (), a first feeder portion (), a second dipole () and a second feeder portion (). The first feeder portion is coupled to the first dipole at two locations a feeder length distance apart. The second feeder portion is coupled to the second dipole at two locations the feeder length distance apart. The feeder portions are also coupled to an antenna terminal (). Impedance at the antenna terminal is determined, at least in part, by the feeder length distance. Each of two end portions of the first dipole distal from the first feeder portion is connected to a respective corresponding end portion of the second dipole distal from the second feeder portion, the first and second dipoles thereby forming a rectangle. The antenna is symmetrical about both a major and a minor axis of the rectangle.

RFID tag and RFID tag antenna

In some embodiments, a power supply slew rate detector may include a filter circuit having a capacitive element operably coupled to a power supply output provided to a flash memory circuit and a resistive element operably coupled to the capacitive element and to ground, and a Schmitt trigger including an input operably coupled to a node between the capacitive element and the resistive element, the Schmitt trigger further including an output configured to indicate a slew rate of the power supply output.

Power supply slew rate detector

A method with a circuit that includes a memory () coupled to an analog line coverage circuit (). The analog line coverage circuit includes a plurality of buffers (-) in which each buffer is coupled to one memory location of the memory, a plurality of bin cells (-) in which each bin cell is coupled to a buffer, a multiplexer (), each input terminal of which is coupled to a bin cell, and an analog-to-digital converter () coupled to the multiplexer and to an output terminal of the analog line coverage circuit. The analog line coverage circuit stores an analog voltage that is representative of a number of occasions that a memory location is accessed, and outputs a signal indicative thereof. A processor (), coupled to the memory and to the analog line coverage circuit, enables the analog line coverage circuit when the processor is in a debug mode.

Code coverage circuitry

A testing circuit in an integrated circuit indirectly measures a voltage at a node of other circuitry in the integrated circuit. The testing circuit includes a transistor having a control electrode, a first conducting electrode coupled to a first pad, a second conducting electrode coupled to a terminal of a power supply, and one or more switches for selectively coupling the control electrode to one of the node and a second pad. A method includes determining a relationship between drain current and gate voltage of the transistor when the control electrode is coupled to the second pad. A voltage at the node is determined by relating the current through the first conducting electrode of the transistor when control electrode is coupled to the node.

Circuit and method for measuring voltage

A sense amplifier () includes first and second inverters (and). The first inverter has an input terminal () and an OUT_B output node and a first transistor (). The second inverter () has an input terminal () and an OUT output node and a second transistor (). The OUT_B output node of the first inverter is coupled to an input terminal of the second inverter, and the OUT node of the second inverter is coupled to an input terminal of the first inverter. The sense amplifier does not use a reference current; therefore, the sense amplifier does not need a reference current generator. The sense amplifier needs only one enable signal to reset a latch () of the sense amplifier. When coupled to a non-volatile memory element, voltages at the output nodes are indicative of a logic level of a bit stored in the non-volatile memory element.

Sense amplifier circuit

A circuit includes a memory () coupled to an analog line coverage circuit (). The analog line coverage circuit includes a plurality of buffers (-) in which each buffer is coupled to one memory location of the memory, a plurality of bin cells (-) in which each bin cell is coupled to a buffer, a multiplexer (), each input terminal of which is coupled to a bin cell, and an analog-to-digital converter () coupled to the multiplexer and to an output terminal of the analog line coverage circuit. The analog line coverage circuit stores an analog voltage that is representative of a number of occasions that a memory location is accessed, and outputs a signal indicative thereof. A processor () is coupled to the memory and to the analog line coverage circuit, and the processor enables the analog line coverage circuit when the processor is in a debug mode.

A charge pump circuit () includes a charge pump (), and clocking circuitry that includes a clock generator () and a bypass circuit (). The clocking circuitry generates clock signals and higher frequency alternative clock signals, for driving the charge pump. Upon start-up of the charge pump circuit and depending on a present value of an output voltage of the charge pump, the clocking circuitry couples to the charge pump either the alternative clock signals and not the clock signals, or the clock signals and not the alternative clock signals. Prior to completion of start-up of the charge pump circuit, at least two rows of pump unit cells are driven by a same alternative clock signal, thereby causing a pump unit cell in a row to charge/discharge at a same time as another pump unit cell in another row, thereby decreasing a start-up time of the charge pump circuit.

Charge pump circuit with fast start-up

A method and apparatus are described for providing a current mirror type high voltage switching circuit () having a reference branch (M, M, R) and a tracking branch (M, M), where the output peak current is limited by adding an additional branch (M, M) to the current mirror circuit which includes an additional mirror transistor (M) and cascode transistor (M), and where over voltage protection is provided by including a shut-off circuit (Q, Q) which turns 'OFF' the cascode transistors (M-M) whenever the output voltage (Vout) exceeds the first reference voltage (Vbat) by a predetermined amount.

High side high voltage switch with over current and over voltage protection

A charge pump system () includes a charge pump (), and a regulator () that includes a clock generator () for providing a clock signal, a control logic () coupled to the clock generator, and a comparator () coupled to an output of the charge pump. The comparator includes a plurality of interleaved latches (and) driven by a single differential () stage that compares the output voltage and a reference voltage. The control logic provides timing signals to cause each latch to perform a latch action at different points in time within each period of the clock signal, each point in time equally spaced apart. An output from each latch is coupled to an output stage (). An output signal from the output stage regulates an output voltage from the charge pump. In one embodiment, the charge pump is coupled to a flash memory ().

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Campinas, Brazil

Walter Luis Tercariol