Avago Technologies General IP (singapore) Pte. Ltd.

Agilent Technologies, Inc.

Avago Technologies Wireless IP (singapore) Pte. Ltd.

Avago Technologies General IP Pte, Ltd.

Walter J Dauksher

Atul Goel

R Shane Fazzio

Wayne Patrick Richling

William S Graupp

Adam Gallegos

Dennis H Eaton

Pedro F Engel

A chip package and methods of manufacturing the same are disclosed. In particular, a chip package comprising a ball grid array is disclosed in which the chip package includes a package substrate supporting the ball grid array and in which the chip package further includes a warpage control frame that helps to minimize or mitigate warpage of the chip package.

Substrate warpage control using external frame stiffener

A design methodology reduces electromigration in integrated circuit joints such as flip-chip bumps by seeking to produce a more uniform current distribution at the interface between the integrated circuit pad and the joint while maintaining an interface form that coincides with standard integrated circuit designs is presented. The design methodology addresses the current distribution at the pad by dividing current carrying traces into a plurality of sub-traces with known resistances such that each sub-trace distributes a known amount of current to the pad of the integrated circuit. The multiple sub-traces connect to the pad and are placed to obtain a desired uniformity in the incoming current distribution. Width and/or length adjustments could be made to each of the plurality of sub-traces to obtain the desired resistances.

Trace design to minimize electromigration damage to solder bumps

An electronic device and transducer structures are described.

Transducers with annular contacts

Transducer structures having multiple piezoelectric layer and annular contacts are described.

Multi-layer transducers with annular contacts

A design methodology reduces electromigration in integrated circuit joints such as flip-chip bumps by seeking to produce a more uniform current distribution at the interface between the integrated circuit pad and the joint while maintaining an interface form that coincides with standard integrated circuit designs is presented. The design methodology addresses the current distribution at the pad by introducing an intermediate trace routing design between the current delivering trace and the pad that distributes the inflow of current from the trace to multiple points of entry on the pad. The intermediate trace routing design includes an outer trace channel connected to the current delivering trace. A plurality of conductive trace leads connect the outer trace channel to the pad. Preferably, each of the plurality of conductive trace leads is characterized by a respective trace impedance so as to distribute equal current flow through each of the leads to the pad.

A novel pad structure for an integrated circuit component that utilizes a bump interconnect for connection to other integrated circuit components that produces a relatively uniform current distribution within the bump of the bump interconnect is presented. The pad structure includes an inner pad implemented on an inner conductive layer of the integrated circuit component, an outer pad implemented on an outer conductive layer of the integrated circuit component, and a plurality of vias connecting the inner pad and outer pad. The outer pad is sealed preferably around its edges with a passivation layer, which includes an opening exposing a portion of the outer pad. The vias connecting the inner pad and outer pad are preferably implemented to lie in a via region within the footprint of the pad opening.

Routing design to minimize electromigration damage to solder bumps

A device having features for enhancing the cooling of an electronic package subject to laminar air flow. The features include a bluff body, located adjacent the electronic package and within the laminar air flow, for creating turbulence in the air flow to enhance the cooling of the package. The turbulence creates a greater cooling effect of the air flow on the electronic package, and the bluff body can include a rod or other structure mounted adjacent the electronic package. The bluff body can also be mounted on the electronic package or on a heat sink mounted on top of the package.

Device for enhancing the local cooling of electronic packages subject to laminar air flow

A device that reduces the interfacial stress caused by differential thermal expansion in an IC/PC board assembly can be created by attaching an annular part, that has a higher coefficient of thermal expansion, to the IC at an elevated temperature. When the assembly cools the annular part contracts and compresses the IC, increasing the change in size of the IC and reducing the stress in the IC/PC joint.

Growing community of inventors

Fort Collins, CO, United States of America

Walter J Dauksher