Motorola Corporation

Nxp Usa, Inc.

Walter J Ciosek

Patrice M Parris

Bruce L Morton

Mark S Aurora

Mark Douglas Hall

Robert T Smith

David Russell Tipple

Robert Eugene Smith

A package to die connection system and method are provided. The system includes a semiconductor device having a substrate with a top surface. A gasket is affixed to the top surface of the substrate and has at least one cavity with a portion of the cavity open to a sidewall of the gasket. A semiconductor die is attached to the top surface of the substrate. A sidewall of the semiconductor die is abutted with the sidewall of the gasket. A portion of a metal layer is exposed to the open portion of the cavity. A pillar located in the cavity is electrically connected to the exposed portion of the metal layer.

Package to die connection system and method therefor

A ROM embedded in a multi-layered integrated circuit includes rows of transistor memory cells. For reduced area, each transistor in a row optionally shares a terminal with an adjacent transistor in the row, whereby adjacent transistors share one of a source and a drain. A plurality of contact lines one each connected to each common terminal, serve as address terminals for cells. A plurality of metal layers are connected to the other of the drain or source terminals by filled vias and include a final metal layer defining a metal pad for each of the other terminals. Filled vias couple selected metal pads to selected signal lines to provide &ldquo;1&rdquo; outputs from selected cells and signal lines which are not coupled by filled vias to the metal pads provide &ldquo;0&rdquo; outputs from selected cells.

Ultra-late programming ROM and method of manufacture

A ROM embedded in a multi-layered integrated circuit includes rows of transistor memory cells. For reduced area, each transistor in a row optionally shares a terminal with an adjacent transistor in the row, whereby adjacent transistors share one of a source and a drain. A plurality of contact lines, one each connected to each common terminal, serve as address terminals for cells. A plurality of metal layers are connected to the other of the drain or source terminals by filled vias and include a final metal layer defining a metal pad for each of the other terminals. Filled vias couple selected metal pads to selected signal lines to provide &ldquo;1&rdquo; outputs from selected cells and signal lines which are not coupled by filled vias to the metal pads provide &ldquo;0&rdquo; outputs from selected cells.

Growing community of inventors

Austin, TX, United States of America

Walter J Ciosek