Motorola Corporation

Freescale Semiconductor,inc.

Walter H Kehler

Rajesh H Zele

John Wayne Simmons

Richard B Meador

Keith Andrew Tilley

Norman T Rollins

Kenneth A Hansen

Joseph E Phillips

Gary A Kurtzman

Nihal J Godambe

A system comprising a voltage controlled oscillator is disclosed. The voltage controlled oscillator includes a single input, a power input, and an oscillation input. The oscillation input is coupled to a amplitude detection device, which in turn provides an indication of an amplitude of the output of the VCO to a threshold detect module. Based upon the threshold detected at the threshold detect module, a threshold indicator is provided to a voltage supply module. The voltage supply powering the voltage controlled oscillator is varied, based upon a value of the threshold indicator.

Self-calibrating oscillator system

A receiver includes a main loop ( ) having a main VCO ( ) and a secondary loop ( ) having a secondary VCO ( ). The receiver momentarily phase locks an incoming RF signal ( ), and then samples and stores a correction voltage ( ) being applied to the main VCO ( ). The main loop ( ) is then put into a non-phase locked mode of operation and the stored correction voltage is applied through a receive automatic tuning circuit ( ) to the main VCO ( ) for the duration of the incoming RF signal ( ). This effectively calibrates the LO frequency ( ) of the receiver to the incoming RF signal frequency ( ).

Method and apparatus for calibrating a local oscillator in a direct conversion receiver

A receiver includes a main loop (222) having a main VCO (210) and a secondary loop (224) having a secondary VCO (216). The receiver momentarily phase locks an incoming RF signal (228), and then samples and stores a correction voltage (240) being applied to the main VCO (210). The main loop (222) is then put into a non-phase locked mode of operation and the stored correction voltage is applied through a receive automatic tuning circuit (218) to the main VCO (210) for the duration of the incoming RF signal (228). This effectively calibrates the LO frequency (230) of the receiver to the incoming RF signal frequency (228).

Method and apparatus for calibrating a local oscillator in a direct

A single-chip transceiver integrated circuit (100) has multiple on-chip circuits that implement receiver functions, transmitter functions, and audio processing functions. The IC (100) has interfaces (220, 240, 252, 270, 260, 245, 288, 290) which are situated among the on-chip circuits, and which couple one on-chip circuit to another. At least some of these on-chip interfaces (220, 240, 245, 252, 270) are configurable to couple an off-chip processing circuit to substitute for a corresponding on-chip circuit. In the preferred embodiment, the single-chip transceiver IC (100) supports radio configurations having off-chip versions of corresponding on-chip circuits for performing receiver front-end functions, synthesizer functions, reference oscillator functions, and audio processing functions.

Configuration single chip receiver integrated circuit architecture

A radio (100) having an integrated transceiver circuit (102) avoids circuit crosstalk through the use of a clock shifter circuit (120). The radio includes a microcontroller unit (MCU) (104) controlled by a MCU clock. A channel selector (116) coupled to the MCU (104) provides a selected frequency channel while memory (106) downloads channel information which includes integer clock shifter ratios assigned to each channel. The integrated transceiver (102) includes a clock shifter circuit (120) which divides a reference signal into a clock frequency and provides this clock frequency to the MCU (104) as the MCU clock. The MCU (104) reprograms the clock shifter circuit (120) with one of the integer clock shifter ratios to generate a shifted MCU clock frequency if the selected frequency channel is susceptible to harmonics of the MCU clock.

Apparatus for clock shifting in an integrated transceiver

A detector circuit (100) for detecting signaling information transmitted with a radio frequency (RF) signal for interpretation by a radio receiver includes a first low pass filter (105) for filtering demodulated audio signals that are directly coupled thereto and for providing a first filtered signal. A second low pass filter (109) is directly coupled with the first low pass filter (105) for filtering the first filtered signal and providing a second filtered signal. A signaling detector (111) is then directly coupled with the second low pass filter (109) for determining the frequency and/or bit code of signaling information included in the second filtered signal.

Direct-coupled signaling receiver with PL/DPL detector

A sampled data filter (400) provides on-chip blocking of DC signals. The addition of a very long time constant (VLTC) integrator (412) into the negative feedback path (414) of a first sampled data integrator (402) provides a lower corner frequency (502) with a zero at DC. The lower corner frequency (502) is adjustable while the desired frequency response is maintained.

DC blocking apparatus and technique for sampled data filters

A squelch circuit (118) is provided having a squelch hysteresis window for preventing squelch chatter in a communication device (100). The communication device (100) includes a plurality of squelch states. The squelch circuit (118) comprises a first means (206) for sensing when the communication device (100) is in a first squelch state. The squelch circuit (118) also includes a second means (116) which is responsive to the first means (206) for varying the squelch hysteresis window to prevent squelch chatter.

Method and apparatus for prevention of squelch chatter

A squelch circuit (200) having an input is provided including a programmable high pass filter (206) for filtering the input signal to produce a filtered signal. The filtered signal is rectified via a differential rectifier (201) to produce a rectified signal. The squelch circuit (200) also includes a threshold comparator (323) coupled to the differential rectifier (201) for sensing when the rectified signal exceeds a squelch threshold.

Comparator switched squelch rectifier

The period of time that the squelch circuit maintains a radio receiver's audio amplifier active after the signal strength of a received carrier fades below a threshold level is inversely proportional to the strength of the received carrier immediately before the fade. This threshold level is also variable. If, immediately before the fade, the received signal strength exceeds a predetermined trigger level (Vtrg) the threshold level is raised. A buffer amplifier (102) charges a capacitor (C) to a voltage which is proportional to the strength of a received carrier. If the carrier fades below a threshold (Vth2 or Vth3, the buffer is disabled and the capacitor slowly discharges through a resistor (R). When the voltage at the capacitor crosses a reference voltage (Vref1) the output of a comparator (104) switches, thereby deactivating the receiver's audio amplifier. If the voltage at the buffer output is within a specified range, a feedback control circuit (112) switches a variable hysteresis feedback circuit (110) such that the negative-going threshold of the comparator (106) is switched from one threshold level (Vth2) to another (Vth3).

Squelch circuit with variable squelch tail and variable hysteresis

An automatic voltage-controlled oscillator (VCO) current control circuit, that senses a voltage in the VCO representative of the current of the VCO, compares that voltage to a reference voltage, and applies the voltage resulting from that comparison back to the VCO at a point therein that changes its bias state in such a manner as to maintain the noise level in the VCO at a minimum and also maintains the power output of the oscillator substantially constant.

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Sunrise, FL, United States of America

Walter H Kehler