International Business Machines Corporation

Walter H Henkels

Wei Hwang

Rajiv V Joshi

Sang Hoo Dhong

Terry I Chappell

Nicky C Lu

Albert Thomas Williams

A hardware design technique allows checking of design system language (DSL) specification of an element and schematics of large macros with embedded arrays and registers. The hardware organization reduces CPU time for logical verification by exponential order of magnitude without blowing up a verification process or logic simulation. The hardware organization consists of horizontal word level rather than bit level. A memory array cell comprises a pair of cross-coupled inverters forming a first latch for storing data. The first latch has an output connected to a read bit line. True and complement write word and bit line input to the first latch. A first set of pass gates connects between the true and complement write word and bit line inputs via gates and the input of said first latch. The first set of pass gates is responsive to a first clock via a second pass gate. A pair of cross-coupled inverters forms a second latch of a Level Sensitive Scan Design (LSSD). The second latch has output connected to an LSSD output for design verification. A second pass gate connects between the output of the first set of pass gates and the input of said first latch. The second pass gate is responsive to said first clock. A third pass gate connects between the output of said first latch and the input of said second latch. The third pass gate is responsive to a second clock. The first and second clocks are responsive to a black boxing process for incremental verification.

Provably correct storage arrays

A low-power pulse-to-static conversion latch circuit is disclosed. The circuit includes self-timed control and an n-bit latch array both designed utilizing self-resetting CMOS circuit techniques. The self-timed feature of the control requires only one system clock input. The evaluation, reset and write-enable controls are all generated within a control macro. The latch is level sensitive scan design (LSSD) compatible and complies with self-resetting CMOS (SCRMOS) test modes. Use of these latches facilitates the synchronization, pipelined operation, power-management, and testing of advanced digital systems employing a mix of static and dynamic circuits to achieve high performance.

Pulse-to-static conversion latch with a self-timed control circuit

A two transistor one capacitor DRAM cell configured with respect to a bit line pair and a single word line in which the gates of the two transistors are connected to the single word line and one of the source/drains of each transistor is connected to a respective electrode of the capacitor and the other of the source/drains of the transistors is connected to a respective bit line of a complementary bit line pair. The storage capacitor is a three dimensional structure with both electrodes being electrically well isolated from electrodes of all other cell storage capacitors. A stacked in trench cell fabrication design is disclosed having a buried strap for connecting the outer electrode to a diffusion region of one transistor and a surface strap for connecting the inner electrode to a diffusion region of the second access transistor.

Method of forming a buried-sidewall-strap two transistor one capacitor

A single sequential timing chain provides inadequate precision of reset-pulse timing and inadequate reset-pulsewidth control for high-performance memories or register files incorporating dynamic circuits. Also, in such circuits, an inevitable lengthening of pulses, from input to output, ensues. These shortcomings are eliminated by the disclosed multiple-branch circuits, which provide for the generation of appropriate control pulses, and by employment of evaluation-path pulsewidth-shortening circuits appropriately interconnected to the control-generation circuits.

Reset and pulse width control circuits for high-performance multi-port

Method of making buried-sidewall-strap two transistor one capacitor

A high-performance register file is implemented in a multi-block structure consisting of sub-arrays and associated multiplexing circuits. For a given port, the outputs of all multiplexer circuits are dotted together to form a single global output. The multiplexer circuits may be completely external to the cells ('standard' approach), or distributed and integrated into the cells ('alternate' approach). The register cells arranged as such, may or may not contain extra latches, pass gates, and controls arranged so that the file may be fully tested via LSSD.

Cells and read-circuits for high-performance register files

A complementary MOS one-capacitor dynamic RAM cell which operates with a non-boosted wordline without a threshold loss problem and which includes one storage capacitor and n- and p-type transfer devices connected to the storage capacitor which function as two complementary transistor devices having gates controlled by complementary signals on the RAM wordlines.

Complementary metal-oxide-semiconductor transistor and one-capacitor

A superconducting memory cell which includes a single Josephson junction or write gate disposed in a superconducting loop having improved sense margins is disclosed. The improved sense margins are achieved by fabricating the superconducting loop so that first and second branches thereof have different inductances. In a specific example, a first branch containing the single Josephson junction has the higher inductance. Still more specifically, the inductance of the first branch containing the Josephson junction or write gate is twice as great as the inductance of the other branch when the I.sub.min of the write gate is zero. In addition, another Josephson junction or sense gate must be disposed in electromagnetically coupled relationship with the second branch of the loop, and binary information must be stored in the form of clockwise and counterclockwise circulating currents of equal magnitude. Writing and reading are accomplished by coincident currents being applied to the cell. A cell having a single control current in addition to a gate current for coincident current selection of a desired cell is shown. A similar cell having at least another control current in addition to the previously mentioned control current and a gate current for coincident current selection is also disclosed. The latter cell, embodied in array form, has a plurality of horizontally disposed control lines each of which intersects a row of memory cells. In addition, a diagonally disposed control line intersects the write gates of adjacent cells which are disposed in diagonally spaced relationship with each other. Arrays which include diagonal control lines have improved write margins and, if they conform to the criteria outlined above, they also have improved sense margins.

Josephson memory cells having improved NDRO sensing

Superconducting devices comprising at least a pair of Josephson tunneling junctions and means for providing a large kinetic inductance interconnecting the pair of Josephson junctions are disclosed. The kinetic inductance is obtained by providing, as a portion of the device, a superconducting element having a thickness much less than its penetration depth. The high inductance devices provided by this means permit an overall increase in device packing density and power reduction, not obtainable with conventional structures. The resulting devices have enhancement ratios of at least one.

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Putnam Valley, NY, United States of America

Walter H Henkels